Design And Verification Of CORDIC-based FFT Processor

The beam-forming is an important step of array signal process, pointing to a direction ofthe maximum beam output obtained by linear combination processing on the received arraydata. Has a key role in the beamformer performance on the sonar, radar and other systemspositioning accuracy, processing capacity and anti-jamming capability. In this thesis, a keycomponent of imaging sonar system beamformer FFT processor features, in depth analysis ofthe FFT algorithm flow, the introduction of the CORDIC algorithm to simplify the complexmultiplication operation FFT processor, FPGA based platform designed and implemented.The overall design through timing simulation and hardware testing, running speed of90MHz,fast processing speed, high-precision arithmetic, to meet the needs of the sonar imagingsystem.The thesis analyzes the basic principles and processes of the CORDIC algorithm andbase2, base4time domain FFT algorithm. CORDIC algorithm and base4time domain FFTalgorithm, pipeline technology, design and implement a CORDIC based FFT processor. TheFFT processor5butterfly algorithm the butterfly algorithm at all levels between a pipelinestructure, able to complete the1024point FFT operation.In order to meet the reliability requirements of the imaging sonar system, the applicationVMM verification technology, combined with a variety of authentication technology, to buildhierarchical high reusable, highly automated functional verification platform. A morecomplete functional verification of the FFT processor FFT processor system-level verification,line coverage reached100%the conditions coverage reached96.34%, the state machine100%coverage, the composite score reaches97.67%, which improves the reliability of the FFTprocessor.