Flexibly Configurable Architecture For Large Number Operation

The large amount of calculation in encryption based on the operation of large numbers slows the encryption speed, designing a hardware accelerator is a way to solve this problem. However, the existing accelerator is low configurable and inflexible. To improve the flexibility, a novel hierarchical architecture of large number is proposed. The new architecture is highly configurable and has better performance, besides hardware resource reuse reduce the resource overhead.The new architecture consists of4layers:application layer, function layer, auxiliary operation layer and hardware resource layer. Every layer can be configured as hardware implemention or software implemention. If one layer is configured as software implemention, every function module can be configured as implemention or not (function select configurable). The new architecture can be configured as four different implemention mode according to the implemention fo every layer, the four mode are:one-layer hardware&three-layer software mode, namely one layer (hardware resource layer) is hardware and three layers (application layer、function layer、 auxiliary operation layer) are software; two-layer hardware&two-layer software mode, namely two layers (auxiliary operation layer and hardware resource layer) are hardware and two layers (application layer and function layer) are software; three-layer hardware&one-layer software mode, namely three layers (application layer、function layer and auxiliary operation layer) are hardware and one layer (hardware resource layer) is software;all layers are hardware. this paper implements one-layer hardware&three-layer software mode and three-layer hardware&one-layer software mode to prove the excellence of the architecture. First, we use one-layer hardware&three-layer software mode to accelerate RSA and ECC. In this experiment the area of hardware is only0.15mm2, but it not only can accelerate RSA, but also ECC. When work frequency is60MHZ,4DSP Parallel execution can accelerate RSA24times, making the encryption time shorten to0.5s. Acceleration performance change better when the length of module change longer. Second, we use three-layer hardware&one-layer software mode to accelerate RSA. This experiment use resource-reuse technology, the performance of RSA accelerator is2times faster for the application of modular frequent change under14%area overhead.The two experiments show that the new architecture has the following characteristics:low resource overhead, high performance,key length configurable, implementation mode configurable and function module configurable. These characteristics broaden the range of applications of this new architecture, shorten the development cycle.