Research And Implementation Of Configurable Verification Environment

With the rapid development of integrated circuit industry,more and more complex functions are integrated on chip.Data research shows that nearly four fifths of chip development time is focused on chip verification.Therefore,it is an important goal to break through the current difficulties of verification and improve the development efficiency of design and verification environment.In the design of the chip,the reuse IP is used to integrate the system on chip to improve the development efficiency.Parametric design is an important way to realize IP reuse.The standardized and parameterized design scheme allows different parameters to be used to configure the hardware IP and integrate it in different on-chip system projects to accelerate the development of the chip.Similarly,parameterized and configurable verification environment can effectively shorten the verification cycle.In this thesis,a configurable parameterized verification environment with self adaptability is proposed.The core of the configurable verification environment is adaptability,which means that when the design parameters change,the verification environment will change adaptively,and the verification environment will be configured to meet the new functional verification requirements.The adaptive verification environment proposed in this thesis is based on the UVM verification framework.By exploring the traditional methodology,an info mechanism compatible with UVM verification system is proposed.Around the PCIe architecture,the function verification is carried out,and the info architecture with tree topology is developed.In the process of realizing highly configurable adaptive verification environment,the thesis studies and analyzes the PCIe architecture,including the PCIe bus topology,address space,transaction transfer mode and other technical content.Aiming at the PCIe architecture,the parameter information of key function verification points in hardware design is extracted,the design parameter model is built and integrated into the UVM environment.Based on the design parameter model,the hierarchical info system with similar tree topology structure with PCIe architecture is built.This thesis analyzes the function verification points of PCIe transaction sequence,makes verification strategy,designs UVM verification components using info mechanism and parametric model,defines coverage groups and coverage points,and finally completes the complete verification of function points of PCIe bus interface transaction sequence.The purpose of setting up a verification environment for the function points of PCIe transaction order is to illustrate the specific application scenarios and advantages of the adaptive verification environment.The advantages and disadvantages of highly configurable adaptive verification environment are discussed by analyzing the verification process and results of the transaction sequence of PCIe bus interface.The results show that the functional verification environment of PCIe transaction sequence can completely adapt to hardware design only by modifying part of parameter information,and the resources invested in later maintenance are very small.For the verification environment of other function verification points,each time a PCIe device is added,the efficiency of writing a new testbench can be increased by 10 times,and optimizing the relevant UVC can save a third of the time.The verification environment plays a significant role in optimizing and universalizing the verification components and promoting the automatic verification process.After the actual implementation of the verification project,it shows that the verification environment is an efficient,high-quality and reusable verification structure.This thesis proposes a highly configurable adaptive verification architecture for multiplexing IP,which can effectively shorten the verification cycle,improve the verification efficiency and optimize the verification process.