| With the development of modern military applications and marine research, underwater sonar systems have extensive applications in many fields. Three-dimensional (3D) sonar system uses transducer array gathering the backscattered signals and beamforms in thousands of directions to obtain real time detection information of target. However, high-resolution3D sonar system is faced with serious problems to be solved like a huge amount of beamforming algorithm computation, and complex and costly hardware circuits.This thesis develops a FPGA design to complete large scale beamforming processing based on distributed hardware architecture using a Virtex-6FPGA and Spartan-6FPGAs.Firstly, by subdividing the48x48planar transducer array into two subarrays:the first-level6x6subarray and the second-level8X8subarray, distributed beamforming greatly reduces90%of the computational load and the storage requirements of phase shift parameters to meet the needs of high-resolution and real-time indicators. The12signal processing daughter boards use24Spartan-6FPGAs to collect2,304channels’ data, DFT transform and parallel complete the first-level subarray beamforming. While the mother board uses a Virtex-6FPGA to complete the second-level subarray beamforming. FPGA design is implemented in pipeline operation structure to beamform in128x128directions.Finally, with help of mathematical software MATLAB, online debugging tool ChipScope and dedicated hardware test platform, repeated tests are taken into each FPGA’s data processing flow. FPGAs’ functional correctness and stability is test and verified. Beams are imported into MATLAB to verify the correctness of FPGA distributed beamforming. Using FPGAs to achieve distributed beamforming overcomes the intractable difficulties of huge amount of computation and complex hardware structure, and has important application value. |