Design Of FPGA Fault-tolerant System Based On Dynamic Reconfisuration

In recent years, the Single Event Effect (SEE) of SRAM-based FPGA has becomeone of the main reasons causing the malfunction of the Space Electronic Instrument. Amass of mitigation methods are taken by the researchers, such as Triple ModularRedundancy (TMR) and Double Modular Redundancy (DMR). Generally, themitigation methods enhance the reliability by increasing integration scale or slowingdown the system frequency. Therefore, the quantitative analysis and reliable evaluationis necessary. Since the single-particle irradiation experiment is expensive andtime-consuming, verification method based on fault-injection is catching moreattention.This thesis carried out the following research: first, the SEE Error Model of FPGAunder the Space Radiation Environment is analyzed; the experimental data show thatconfiguration memory is the most vulnerable of the SEE. Then, the basiccharacteristics of SRAM-based FPGA and configuration principle are introduceddeeply. Finally, the test platform of FPGA configuration information upset based ondynamic reconfiguration is developed, which can test the ability of circuit anti-rolloverSEU by simulating the configuration information upset to evaluate the reliability of thetesting system.