A Design Of Low EMI Buck DC/DC Converter

With the rapid development of microelectronic technology, electronic equipment has been widely used in various fields. Power management device as a driving force of the chip to electric energy conversion, distribution and real-time monitoring of the whole system, is an important guarantee of efficient and stable operation of power system. In order to make the power can be more efficient and reasonable management, different the requirements and development specific power management chip for different application fields is one of the current trends. In this paper, based on the practice of engineering project has developed a low EMI buck DC/DC converter chip for the car’s electronic equipment, completed the circuit design and physical implementation of the chip.Through the study and comparison of the mainstream buck DC/DC switching converter control mode, according to the application requirements of the chip, adopts the PWM control mode with peak current mode feedback, making the system achieve faster load response speed, at the same time, through the real-time detection for the peak current provides overcurrent protection to prevent damage caused by chip load current exceeding the normal work scope for the circuit. Working in heavy load and high duty cycle mode are easy to produce the situation of sub harmonic oscillation, as a result, take a first-order linear slope compensation to enhance the stability of the system. By adopting the technologies of synchronous rectification model topology structure, overcomes the diode rectifier to bring the conduction losses, so that the system efficiency is improved. And according to the application environment for reducing electromagnetic interference needs, pulse width modulation control mode under fixed frequency work is easy to generate larger electromagnetic interference, overcoming the defect by using spread spectrum clock technology. The spread that spectrum of the clock signal in a certain range of broadening greatly weakened the peak noise gain of clock signal to nearly 20 d B. Reducing the electromagnetic interference of switching power supply chip has important significance for the stability of internal modules of the whole system. In addition to the test requirements of high integrated circuit on the chip increase the circuits designed for testability, so that some key signals inside can be measured more conveniently and reliable, which can shorten the test cycle and improve the efficiency of testing.Circuit design of the whole chip is completed under the Cadence platform, and the circuits of the sub modules are designed and simulation verified. Finally on the characteristic index of the whole system simulation completed corresponding to the input voltage in the range of 2.5V~5.5V, up to 3A current. Chip layout design based on the standard 0.35 μm COMS process by using virtuoso layout design tool under Cadence platform, combined with the function description of the sub modules and semiconductor manufacturing technology giving the chip layout plant and rout selection and the layout design of on-chip integrated switch and synchronous power MOSFET. The chip is currently taped out.