Design Of A Low-power High-Stability LDO Linear Regulator

In the recent years, with the rapid development of the integrated circuit industry, mobile phone, PAD, digital cameras and other portable consumer electronic products become much more popular and developed. However, every kinds of the electronic products has to face a problem that how to manage the power source efficiently to extend the service life and improve the performance. This question has put forward higher requirements to the power management chip and how to design a low power, low cost and high performance PMU chip has become a hotspot of the industry. LDO linear regulator is a commonly used PMU chip which has many advantages comparing with others. Such as low quiescent power consumption, low noise and low cost. Based on these advantages, LDO is widely used in various types of consumer electronics and industrial fields.The paper designed a LDO which is applied to the PMU in the MCU to meet the low power application. The LDO includes Bandgap, Error amplifier, Power transistor and the Feedback network. The over-current protection module is also added as the auxiliary circuit to protect the chip when the load current is too large. The whole design has been optimized to meet the low power requirement. By analyzing and researching on the LDO frequency compensation methods, we use the suitable scheme to keep the loop stable. Finally, we complete the design of layout.The circuit is designed with the 0.13μm LP technology of GSMC. The designed LDO can work in a wide range of voltage(2.7V~5.5V),it can output a stable 1.5V voltage to supply for other analog and digital module.The max load current of the LDO is 200 m A.We use Spectre to simulate the circuit and get the result that the quiescent power consumption of the LDO is less than 15μA, and the phase margin is over 60 degrees. The output voltage is 1.5V and the voltage temperature coefficient is less than 20ppm/℃.We use the trimming signal to eliminate the effect of offset voltage to improve the accuracy. The transient change of the load from light to heavy is less than 100 m V with the external 0.1μF capacitor.We also verify the important norms by PVT. After the pre and post simulation, the results show that the circuit can meet the requirements. The preliminary test of the chips after tapeout shows that the LDO’s performance is qualified.