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Study On Verification And Test Of High-performance Image Compression Chip

Posted on:2015-11-03Degree:MasterType:Thesis
Country:ChinaCandidate:Y Q YaoFull Text:PDF
GTID:2272330464968556Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
With the continuous development of China`s aerospace industry,increasing image data bring difficulties to the data storage and cause the transmission channel a heavy burden.As an important part of the spacecraft, image compression system can compress data effectively. Using high performance image compression chip is conducive to the realization of the system and helps to improve system stability and makes the system have the ability to compress image data in real time.High performance image compression chip implements JPEG2000 algorithm, supports lossless and lossy compression, have 210 MHz maximum working frequency and 105 M Samples/s data processing speed, with scale of more than 40 millions gates and 130 nm manufacturing process. It has the advantages of high processing speed, low power, anti-radiation, etc.It`s a specialized component used in aerospace and meets the requirements of high performance and reliability.This paper mainly researches the chip verification and test, include functional verification, static timing analysis, timing verification and single-event phenomena experiment. Functional verification mainly for chip compressed core, configuration interface, plug-in memory, camera interface, stream interface, chip operating frequency and asynchronous timing, etc. Different verification choose different vectors for test. For the interface, in order to ensure it meets the chip interface specification, wo focus on the interface timing analysis. Primetime extract all synchronous timing paths of the entire circuit, then calculate the total delay of each path based on gate delay and path delay, finally wo get a complete static timing analysis report, then analysis and optimize the timing violation paths. Timing verification sets up a timing testbench, using Netlist and SDF to do the dynamic timing simulation, have acheived succeed validation of asynchronous logic, camera interface, stream interface, SDRAM interface and PLL of the chip.According to the needs of single-event phenomena experiment, we set up an automated test platform, have achieved the function of sending image, comparision, display and storage. Experiments were carried out on two chip, the results show that the first version chip has the problem of single event latchup. Due to the use of new technology, thesecond version chip has the ability of anti-radiation.
Keywords/Search Tags:Functional verification, Timing verification, STA, Single-Event phenomena
PDF Full Text Request
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