Researches And Designs Of Low Power Capacitor-less LDO For Phase Locked Loop

LDO linear voltage regulators are the essential parts of the power management systems in the portable electronic equipment, a low-power, high-performance LDO not only makes the electronic products working environment more stable, but also prolongs the battery cycle.As the development of the SOC, conventional LDO with output capacitor is not suitable for use in the portable electronic devices, so the reseach for on-chip output capacitorless LDO is necessary.In this dissertation,a low-power,capacitorless LDO linear voltage regulator with Slew-Rate Enhancement circuit is proposed. The stability of the whole system is achieved by miller zero-regulator compensation technique, which means Miller capacitor is adopted in this design in order to achieve separation of the main and secondary points, and zero-regulator resistance can move the zero located on the right half plane to the left half plane. A new Slew-Rate Enhancement circuit is proposed,which can increase Slew-Rate during transient response, and improve the transient response.The proposed LDO regulator has been designed and simulated in SMIC 0.18 μm CMOS process.The results of simulation show that with a 1.8V power supply, the output voltage is 1.6V.It can deliver a load current of 200mA at a dropout voltage of 150 mV. It only consumes a quiescent current of 5μA.The regulator achieves a minimum phase margin of 60° at different load current or power supply. The amount of overshoot/undershoot voltage for a load slew-rate of 99mA/1μs is 51 mV and 45mV, the settling time is 1.5μs.Based on the application of LDO regulator, this paper also designed a fast locking charge pump phase-locked loop.Based on dynamic loop bandwidth allocation technology, the proposed PLL can widen the loop bandwidth to accelerate the locking process, as the loop approaches the locking condition,the PLL then adjusts the loop to a narrow bandwidth, as desired in some applications.Thus,the PLL will not introduce a lot of phase noise and the settling time is also reduced.The proposed charge pump PLL has been designed and simulated in SMIC 0.18μm CMOS process.LDO can stabilize the supply voltage for VCO.The results of simulation show that with a 1.6V power supply,the output signal frequency is 640MHz when the input reference signal frequency is 20MHz.The settling time of CP-PLL with the improved structure is 1.5μs.