Design Of Phase-locked Circuit For Digital Gyroscope System

With the continuous development of micro-electromechanical technology and integrated circuit, the demand for MEMS gyroscope will be digital and intelligent.MEMS digital gyro system is divided into mechanical header sections and ASIC interface circuit, and the performance of the interface circuit has important influence on the gyro system performance, thus digital gyro interface circuit has become the focus of many researchers. Phase-Locked loop is realized to generate the clock signal in the system,aimed at digital gyro in the thesis.This thesis discusses the system and the basic operating principle of each module in the system at first, the linear mathematical model is established, the performance of the system are analyzed based on the mathematical model, such as the loop bandwidth,etc. Then discuss the Phase noise distribution and transmission mechanism of each module.On this basis, according to the design index and the effect of loop bandwidth to lock time and phase noise, compromise to consider and calculate the key parameters of the charge pump phase-locked loop, then this thesis uses the Matlab and simPLL to simulates and verifies the calculated system parameters in the behavior model. Using the calculated system parameters and the choosing reasonable circuit structure of each module to completes corresponding design and simulation in Cadence Spectre.The mismatch of current for charge pump circuit is within 1%, and the voltage-controlled oscillator’s phase noise retain the allowance to the final phase noise. After simulating the system, the lock time is 10 ms when the frequency division ratio is 1250.25.The thesis implements the PLL circuit based on huahong 0.35 um process, and completes the layout and use the Calibre and the Spectre to extract layout parasitic parameters and complete the post-simulation.the input signal frequency is 4 KHz, the output signal frequency contain the range of 1~20MHz, considering the parasitic parameters, the lock time is 12.5 ms when the frequency division ratio is 1250.25.And the total phase noise of system is-70.64 dBc/Hz @ 100 Hz,-76.57 dBc/Hz @ 1 KHZ.