Research And Design Of A DC/DC Converter Control IC With A Quadratic Slope Compensation

In the 21 st century, as the improvement of people’s living standard, selectronic communications, digital products develop. Increasing high standards and requirements have been given to these products, such as small size, lightweight, performance, agility and speed. The power supply as integral part of all kinds of electronic products, its performance is also required higher and higher. With the rapid development of technology, high speed and low power consumption, stable large output load current DC / DC converter chip becomes the pursuit of workers.This paper describes the current situation in China and abroad as well as the development of power management IC, and then describe several common peripheral Topology DC/DC converter, two kinds of PWM control mode and the principles and methods of traditional slope compensation. Focus on describeing the innovations of quadratic slope compensation and benefition through a peripheral circuit article. Based on this theory, design a DC / DC converter control IC. Firstly, analyse the whole chip functions and working principle, including pin description and a simple analysis of the control loop, chip benchmark module provides new pre-restructuring, and the reference voltage generation circuit reduce the reference voltage PSRR. One feature of the chip is introduced quadratic slope compensation circuitry to prevent the occurrence of sub-harmonic oscillation system, it has the advantage of greatly reducing the chip size, while preventing excessive compensation of the inductor peak current, thus affecting the chip’s load capacity. Chip error amplifier circuit has the high slew rate, it can quickly respond the changes on voltage feedback to improve the system efficiency. ramp recovery circuit has the high gain and phase margin large, to improve the chip.The CSMC 0.5 μm of using 40 V BCD process simulation files, and using simulation tools such as Cadence and Hspice, to simulate on-chip modules and the overall simulation. Obtained at 7 V input voltage, the output voltage is stabilized 5 V, the result of the output current of 5 A. At the same time, the other parameters and indicators of the chip have reached the requirements.