Study On Multi-channel Synchronization Technology Of High-speed Logic Analyzer

As the main test instrument in data domain,logic analyzer plays an important role in the design and test of digital systems, and it is pretty helpful when used to conduct timing analysis for multiple and parallel datas, such as some parallel buses.In recent years, the operating frequency of digital systems has increased greatly and the width of some parallel buses has also doubled, in order to get a better test performance, the number of available channels and maximum timing sample rate of logic analyzer has also increased and improved. With the number of available channels increasing, synchronization among different channels becomes more and more important, especially when it used to conduct timing analysis for high-speed digital system, the synchronization among different channels will affect the analysis result directly. So, attention should be paied to the study on multi-channel synchronization technology during the design of high-speed logic analyzers, in order to improve the synchronization among different channels.In this paper, study on multi-channel synchronization technology is based on the research and development of high-speed logic analyzer project of laboratory, and more attention is paied to analyze those possible factors, which will affect multi-channel synchronization, and then some possible solutions are proposed.The main works in this paper are as fallows:1. The possible reasons causing channels asynchronism and solutions to realise channels synchronization are discussed.2. A logic analyzer is designed to verify those possible synchronization solutions proposed in this paper are feasible.With the design of a logic analyzer is completed, some test are conducted for its multi-channel synchronization performance and other relevant functions. The results indicate that all functions work well, which verify the multi-channel synchronization solutions and other relevant technics proposed in this paper are feasible.