Hardware Platform Design Of Synchronization Controller Based On FPGA

During operation of accelerator-driven subcritical system(ADS) injector II, a synchronization system is needed to synchronize related equipment in ADS injector II. This paper will illustrate a synchronization controller based on FPGA, which was designed to meet the requirements.The synchronization controller is based on event timing system. It is divided into two parts: master board and slave board. The role of the only master board is to send trigger events to the slave board through the optical fiber. The role of the slave board is to send pulse signals to the related equipment after receiving trigger events. The synchronization controller takes FPGA as the main chip, transmits synchronization events with SFP module, and transmits upper control commands via Ethernet. The slave board uses accurate clock and data recovery chip to recovery reference clock, which is synchronized with the master board reference clock. Meanwhile, the slave board uses digital delay chip to generate trigger signals with adjustable pulse width and delay.In this paper, the main objective is to design a set of synchronization controller hardware to meet the requirements. This paper focuses on hardware design processes. The program design process is also described in this paper. The program is a further test of the hardware, but it also can be applied to the synchronization controller as a complete program. Finally, the synchronization controller is tested in detail in the laboratory. Results showed that the synchronization controller hardware meets the requirements.