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Development Of Digital Delay/Pluse Generator Based On FPGA

Posted on:2019-08-26Degree:MasterType:Thesis
Country:ChinaCandidate:Y Q SunFull Text:PDF
GTID:2382330548459320Subject:Precision instruments and machinery
Abstract/Summary:PDF Full Text Request
Digital delay/pulse generators are also called delayers or synchronizers.It is widely used in laser targeting,nuclear fusion,analytical instruments and other fields.In the Time of Flight Secondary Ion Mass Spectrometry(TOF-SIMS)instrument,The delay/pulse generator provides high-precision synchronization signals for an ion optics system,post-ionization ionization module,secondary ion extraction system,mass analyzer,and data acquisition system,etc.The delay/pulse generator serves as a TOF-SIMS measurement and control system.One of the core components,its performance will directly affect the overall instrument indicators.Based on the project of “National Major Scientific Instrument and Equipment Development Special Projects TOF-SIMS Scientific Device dedicated to isotopic geochronology”,The purpose of this thesis is to develop a synchronization device,which can meet the TOF-SIMS instrument,and which without redundancy and has a simple structure.This thesis according to the TOF-SIMS instrument's request to the time delay performance index,analyzes the factor that affects the time delay/pulse generator performance index,puts forward three feasible technical schemes,compares the merits and the shortcomings of the three,chooses the electric capacity secondary charging technical plan.The program uses FPGA internal counters to achieve digital delays of more than 10 ns,using a ramp circuit to achieve analog delays of less than 10 ns and to compensate for random jitter.The hardware circuit of the delay/pulse generator was developed,including trigger shaping circuit,FPGA module,communication module,analog delay circuit module,human-machine interaction module based on STM32 microcontroller,drive module and power supply module.Among them,the FPGA module includes a jitter processing circuit,a digital delay circuit,and a Nios II soft core MCU.The system control software was developed based on the Nios II soft core MCU.The function configuration,parameter adjustment and data communication of the digital delay circuit and analog delay circuit were realized.The test results show that the self-made delay/pulse generator within 1ms delay range,the external trigger peak-to-peak jitter is less than 500 ps,the self-trigger peak-to-peak jitter is less than 160 ps,the output pulse rising edge is 1.365 ns,and the delay resolution is 100 ps.The indicator meets the expected design and meets the requirements of TOF-SIMS instrumentation for delay accuracy,and can replace imported similar equipment BNC575.
Keywords/Search Tags:synchronization device, FPGA, delay pluse, jitter, TOF-SIMS
PDF Full Text Request
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