Design Of A Buck Converter With Fast DVS Response

The rapid development of potable devices brings higher requirements for the performance and power dissipation of chips. Dynamic Voltage Scaling(DVS) is one of the popular solutions. Howerever, effective DVS system requires that the supply voltage can be changed rapidly. The structure of LDO is relatively simple and has higher response speed but suffers from low efficiency. Therefore, switching power supply becomes a better choice. But how to achieve fast DVS response has always been a big challenge for switching power supply. This paper presents the design method of the voltage mode controlled buck converter with fast DVS response as well as the design and optimization of a buck converter with 5MHz switching frequency. Firstly, this paper focuses on the Type-Ⅲ compensation, studies the effect of the positions of zeros and poles on the loop stability, and gives a design example. In addition, this paper investigates the factors that influence the DVS response of buck converter, including the positions of zeros and poles, duty cycle saturation, inductor current saturation and Pseudo-Type-Ⅲ compensation structure. Then, the design of two chips is presented. They use different Pseudo-Type-Ⅲ compensation scheme. Moreover, one chip is an optimization of another and has improved the performance.The design of the first chip is based on the 0.13μm CMOS standard process. The input voltage range of the buck converter is 2.8V-3.6V. While the output voltage range is 1.2V-1.8V and the maximum load current is 1A. Test results show that when the DVS response occurs, the up-tracking speed is 8.3μs/V and down-tracking speed is 15μs/V. On the other hand, the design of the second chip is based on the 40 nm CMOS standard process. The input voltage range of the buck converter is 2.8V-3.6V. While the output voltage range is 1V-2V and the maximum load current is 1A. According to the simulation results, the up tracking speed is 3.7μs/V and down-tracking speed is 9.3μs/V. A new Pseudo-Type-Ⅲ compensation topology and a nonlinear method which decreases the undershoots during step down response are used in the second chip. Both chips use 5MHz switching frequency, 4.7μF output capacitance and 1.1μH inductance. Finally, the chip verifies the proposed design method of the buck converter with fast DVS response.