A Output-capacitorless Low-dropout Regulator With Fast Response

With the development of medical electronics, sensors, Io T and other electronics, the integration of a chip becoming more and more larger, in order to integrate low-dropout linear regulator(LDO) into the chip and eliminate output filter capacitor in traditional LDO, thus saving the cost of packaging and peripheral components, capacitor- less LDO and the associated circuit design technology has been widely studied.Capacitor- less LDO doesn’t have large output filter capacitor, thereby making the output voltage dynamic error relatively large, when the load switches between the no- load and full- load. In addition, the dominant pole is always locating at the output of EA, which would make the output pole move to the low frequency when the load current is low, thereby causing stability problems.To design a fast response capacitor- less LDO, Firstly, the basic principle of the LDO and its various technical standards are analyzed, and then several common types of capacitor- less LDO in the literature, as well as their improved structure are analyzed, including DFC structure, Q-Reduction structure, FVF structure and dual transistors output stage structure. All of them could improve the stability with light load and speed up the transient response.Reference to the literature, we design a fast response capacitor- less LDO. The design is based on SMIC-0.18μm-CMOS technology. The circuit comprises a sub-threshold reference module, and current bias module. Wherein LDO structure using dual transistors output stage, it can automatically switch the circuit into a two-stage amplifier or a 3-stage amplifier depending on load current. The error amplifier uses split-length MOS structure, in order to introduce cascode Miller compensation. Spectre simulation results show that the quiescent current is 50μA, the minimum allowable output current is 10μA(including the current of feedback resistors). When the load transforms between the light load(5μA) and full load(50mA), the dynamic error of output voltage is less than 100 mV, and both restore stability in 2μs, the LDO can always be stable within the input voltage and output current range.