Research On Key Technology Of LDO With Fast Transient Response

With the continuous development of the integrated circuit industry,the increasing scale of the power management market,and the continuous reduction of chip area,the output of the capacitor-less type low dropout linear regulator(CL-LDO)does not require a large capacitor,which can be extremely reduce the chip package area,makes CL-LDO widely applicable to portable devices such as smart phones,bluetooth headsets,and tablet computers.Due to the loss of the large capacitor structure outside the chip,this design also brings challenges to the stability and transient characteristics of the CL-LDO.This thesis first starts from the basic structure and performance indicators of the LDO,and especially analyzes the stability of the CL-LDO.Since the CL-LDO does not have a large external capacitor for charge storage and filtering,when the load current changes from no load to full load,its output voltage will be unstable.At the same time,the compensation method of CL-LDO is different from that of traditional LDO.The output of traditional LDO has a large capacitance structure,so the main pole is located at the output of LDO,while the main pole of CL-LDO is located at the output of error amplifier,which makes CL-LDO at no load.The stability under the conditions is very poor.In response to the above problems,this article will use the low output impedance characteristics of the push-pull buffer structure,combined with Q-reduction compensation and NMC(Nested Miller Compensation)technology to improve the stability of CL-LDO,and the push-pull buffer structure has a certain improvement in load transient response.Then,in order to further enhance the load transient characteristics of CL-LDO,the advanced transient enhancement technology at home and abroad has been deeply studied and analyzed.Based on this,the output voltage spike detection and adaptive dynamic bias current technology are used to improve two types of load transient enhancement circuits.Among them,the output voltage spike detection network detects the rapid jumps of the CL-LDO output terminal and the gate terminal voltage of the power switch,so that when the load voltage jumps,the gate terminal and the output terminal of the power switch are quickly charged and discharged to reduce the load voltage jump.At the same time,this article designs a bandgap reference circuit,error amplifier,overheating and current limiting protection circuit,and CL-LDO switching circuit for CL-LDO.Among them,protection circuits such as overheating and current limiting can effectively reduce irreversible damage caused by excessive internal temperature of the chip and excessive current.Finally,based on the TSMC 180 nm CMOS process,the CL-LDO designed in this paper is designed and simulated,and the layout of the CL-LDO core circuit is completed.The simulation results show that the input voltage range of the CL-LDO designed in this paper is 2.7-5 V,and the output voltage is stable to output 2.5 V;the output load current range of the circuit is 10 u A-100 m A,and the system loop bandwidth of the LDO under different simulation conditions is greater than 1 MHz.The phase margin is greater than 60°,which meets the stability requirements;the output capacitance is 0-100 p F,the minimum voltage difference is 140 m V under full load,the quiescent current of the CL-LDO system under no load is less than 45 μA,and the power supply rejection ratio is-67 d B at 1 k Hz.In addition,this article adds two load transient enhancement circuits,so that when the load current jumps rapidly between 10 μA-100 m A,the maximum jump amplitude of the CL-LDO output voltage is within 100 m V.