Design And Realization Of Adaptive Anti - Jamming Algorithm For Beidou Navigation Based On

Today, with the rapid development of satellite navigation technology, location service has been integrated into our daily life, navigation is known as the third major industries following the mobile and internet. Satellite navigation plays an irreplaceable role in the maintenance of national security. In order to ensure that the navigation system is not affected by the interference, this thesis studies the realization of adaptive anti-jamming algorithm based on array antenna which applied in the Beidou navigation system.Firstly, in this thesis, it introduces the principle and method of adaptive anti-jamming algorithm. Then, the array model has been simulated in MATLAB, and the spatial and space-time anti-jamming algorithms have been given based on the power inversion algorithm. According to the system’s requiremnets, the anti-jamming algorithm realized by the scheme of FPGA is established, including digital down converter (DDC), weight calculation, data on weighted, digital up converter. According to the different methods of weight calculation module, it provides two kinds of realization methods of anti-jamming algorithm on FPGA: one is based on FPGA embedded soft core NIOS II, applies the process of weight calculation in NIOS II core by using C language; another is to use the hardware description language Verilog HDL to process the weight calculation. In the FPGA, the weight calculation involves the floating point calculation and positive definite Hermite matrix inversion. In this thesis, it gives the realization method and simulation results of each module, and compared with the MATLAB simulation results. Finally, the experimental results of two methods are given. From the result, it demonstrates that the two schemes both have anti-jamming performance, and verifies the correctness of the design.