A LDO Circuit With Dynamically Modulated Strong Miller Compensation With Damping Factor

The stability is the key parameter of a LDO circuit. LDO must generate a stable output voltage under a changing DC input voltage (the wave range of the input voltage is acceptable) to become the power supply of the circuits. Therefore the stability of the LDO is the most important in a LDO design. In order to prevent the LDO circuit from oscillation when the system frequency goes up to a high range, we should make frequency compensation in the LDO circuit. The traditional compensation method is the miller compensation. But under the constraint of the chip area and the variation range of the load current, the effect of the miller compensation is limited. An enhancement miller compensation circuit was put forward by Rincon Mora. The circuit enlarges the effective capacitor by the interaction of the current and voltage magnify together. The circuit reduces the chip area of the compensation capacitor and allows the LDO to drive larger load capacitor. But this structure has same shortcomings, too. The gain-frequency curve of the structure is easy to present resonance peak, so much as to bring a right-platform pole to make the LDO circuit oscillate.When use a traditionally enhancement miller compensation, LDO is hard to keep stable during the whole loading range, from light load to heavy load. Normally, we should do a trade off between light and heavy load. In this paper, we improve the common method of the enhancement miller compensation, in order to make the LDO keep stable during the whole loading range.The LDO circuit of this paper is based on a 0.5u CMOS process, using Cadence EDA tools to design the circuit. Base on the analysis of the principle of the low dropout voltage linear regulator, we design a LDO circuit, whose input voltage range is from 2.5V to 5.5V, dropout voltage is 250mV at 600mA load current. The traditional application of the LDO uses a small load capacitor of 1uF and allows the Resr of the load capacitor changing from 1mΩto 1Ω. The PSRR is 65dB at 1 kHz frequency, and the noise is 30uVrm at 1 KHz. The technical feature of this LDO circuit is the enhancement miller compensation with the damp gene dynamic modulation which guarantees the LDO keep stable during the whole load current range.The whole circuit was designed using winbond 0.5u DPDM CMOS process, and was simulated and validated by HSPICE tools. The thesis finished the mask layer design and layout drawing, pass the DRC and LVS check. After all, the circuit was put in production in winbond TaiWan. After chip probing test and package, the LDO circuit was evaluated in the bench. The circuit is tested in a PCB board, and proven that the electronic parameters of the circuit meet the design spec.The main features of this low dropout voltage linear regulator are: working temperature range: -40°C～125°C, output voltage regulation: error 1.5% at load current of 600mA, and dropout voltage is 0.25V at load current of 600mA.