Design Of Capacitor-Less Low Drop-Out Regulator For SRAM

Static Random access Memory (Static Random access Memory, SRAM) has been widely applied in digital communications in recent years because it has low power consumption, high speed, as well as good compatibility. However, the internal circuit module, such as the sensitive amplifier and Bitcell, puts forward some strict requirements to Power Management Circuit. Low Drop-out regultors play a very important role in the SRAM because it can provide a low noise and a fast transient response while providing clean output voltage.This paper proposes a Capacitor-less LDO used for SRAM based on 65nm CMOS process. The LDO is consisted of High precision and High PSR Voltage Reference and Error Amplifier, as well as Power stage. the second-order curvature-compensation is achieved by using MOS transistors operating in weak inversion region, Besides, A pre-regulation circuit is employed to improve the power supply rejection ratio (PSRR) of the Voltage reference; The error amplifier, designed to be gain variable, can be viwed as a two-stages amplifier when the load is light, at this time, the Cascode Miller compensation is applied to maintain stability; When load current becomes larger, the whole structure switchs itself to a three-stages amplifier, meanwhile, Active feedback frequency compensation is applied to ensure stability.The whole circuit is self-baised and the transient response is enhanced by dynamic biasing. The mechanism of the proposed technique is analyzed thoroughly and the corresponding LDO circuit is implemented in 65nm CMOS technology. Simulation results show that the proposed LDO achieves a 1.230V output at 2.5V supply voltage and a temperature coefficient as low as 12.1 ppm/℃ over the temperature range of -55℃ to 125℃. The circuit also demonstrates very high PSRR and very good line regulation performance, as well as the line regulation. The simulated PSRR at room temperature is -75dB@1kHz and the load regulation is 0.171mV/mA only, meanwhile, the Line regulation is 0.83% only. With the proposed LDO regulator, the amount of undershoot/overshoot in the output voltage under extreme load transients and the recovering time are 117.4mV/76mV and 703ns respectively for a load slew rate of 100mA/300ns, the amount of undershoot/overshoot in the output voltage under extreme load transients and the recovering time are 147mV/91mV and 728ns respectively for a load slew rate of 100mA/100ns Besides, the quiescent current of the proposed LDO regulator is less than 180μA.The proposed LDO regulator, which has a high performance of precision and PSRR, as well as good transient response, can be widely used Power Management module in small SRAM and other digital chips.