| NGB-W is a part of the NGB that playing an important role of wireless services.NGB-W aims to optimize the transmission of the wireless information service by theconvergence of broadcasting network and bidirectional communication network.However, the broadcasting channel is complicated which lead to the signal transmissionserious fading. interleaving technique solve this problem that reduce the signal weakingeffectively, the reduce of channel interference and guarantee of signal transmissionperformance become critical for NGB-W system.with an increasing demand forinterleaving in wireless network, variety of interleaving technology effectively dispersethe relative signal that improving the transmission quality of the input stream, makesure and improve the performance of NGB-W wireless system.In this thesis, the development and principle of the interleaving technique, bitinterleaving, bit de-multiplexing, time interleaving and frequency domain interleavingtechnique are firstly introduced. Then giving detailed algorithm and configurationparameters of bit interleaving, bit de-multiplexing, time interleaving and frequencydomain interleaving in NGB-W. According to the algorithm and the configurationparameters, this paper introduced specific implementation scheme, timing-sequencediagram and input and output ports of the definition. In the bit interleaving, thegenerating method of reading and writing address optimized the bit interleaving to someextent, in order to improve the computing speed, the ping pong operation ideas wereused in bit de-multiplexing. time and frequency domain interleaving using the methodof the state machine and pipeline respectively, this paper adopting the design thought ofTop-to-Down and using Verilog hardware description language to realize the interleaver.The encoding of bit interleaving, bit de-multiplexing, time and frequency domaininterleaving has been studied in this paper. The author used software of Quartus forgrammar compiler, and software of Modersim for function and timing simulation. Thethroughput rate and system clock have been greatly improved in memory from thesimulation diagram. However, the occupancy resources need to be further optimized.Finally verification and simulation will be done on the development platform of FPGA. |
