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Design Of Low Power12-bit Succesive Approximation Register ADC

Posted on:2015-10-28Degree:MasterType:Thesis
Country:ChinaCandidate:X J ZhangFull Text:PDF
GTID:2298330422991560Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of information technology, MEMS sensors are widelyapplied to civil and military electronic fields. And MEMS accelerometers are the workhorses of these sensors in the inertial navigation system. While its performance isinfluenced by the temperature, temperature compensation is an urgent need for MEMSaccelerometer. At present,the methods of compensation are implemented on the basis oftemperature characteristics of accelerometer, and the output of MEMS accelerometer iscompensated according to the measured temperature. For convenient signal processing,it is necessary to transform the analog signal into digital form. Considering itsadvantages of precision, area, speed and power consumption, a successiveapproximation register analog-to-digital converter is the optimum selection for theconversion of temperature signal.In this thesis, the presented SAR ADC system consists of DAC, comparator, timingcontrol circuit, and I2C interface circuit. Firstly, with a further analysis of the energyconsumption of several charge DAC, a Vcm-based capacitor array structure is chosenbecause its advantage of power consumption. Using an attenuation capacitor, the wholecapacitor array is divided into two parts, a high weight part and a low one. In this way,the total area of capacitance is reduced. Secondly, a comparator adopts a combination ofpre-amplifier and latch to improve the comparator’s speed, where a dynamic latch isused to reduce its power consumption. And the comparator offset is calibrated by theuse of output offset calibration technique. Then the timing control part is studied, inwhich a sequencer is applied to produce a group of signals. And the signals can changethe voltage of capacitors by switches and data selectors, implementing the successiveapproximation logic circuit. Finally, each module in I2C interface circuit is designed andverified functionally in Verilog-HDL.According to the simulation, it gets a SFDR of83.7dB and consumes0.62mWunder a sampling frequency of100kS/s and supply voltage of5V.
Keywords/Search Tags:Low Power, Successive Approximation Register ADC, Charge DAC, Comparator
PDF Full Text Request
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