Analysis And Verification Of Noise And Harmonic Distortion Of Fourth-order Feed-forward Sigma-delta Modulator

Recently, the main work about Sigma-Delta modulator is how to increase itsperformance. The noise and nonlinearity of Sigma-Delta modulator can decrease theperformance greatly. Therefore, it is essential to analyze the noise and nonlinearity ofthe modulator. In this dissertation feed-forward Sigma-Delta Modulator is designed, andits the noise and harmonic distortion are deeply analyzed.Firstly the working principle of Sigma-Delta modulator is introduced. Based on theanalysis of models that introduce harmonic distortion in modulator, the non-linearmodels are established in Simulink. Next the noise in the modulator is analyzed andnoise models are also established in Simulink. After considering the target in thedissertation the system level of modulator are established and simulated in Simulink.The full feed-forward and full-differential topology are adopted in this work. Aftersimulating in Cadence on circuit-level, the results are also analyzed.The design of the system level of the modulator is based on the Simulink inMATLAB. In order to decrease the output swings of integrators and improve thestability of the modulator the full feed-forward topology is adopted in the design. Thedesign is capable of digitizing a50kHz baseband signal with the quantization noise146.7dB in Simulink, and the effective number of bits (ENOB) is24bits ideally. Afterconsidering the noise and nonlinear in the modulator the noise floor of the modulator isabout-140dB and the ENOB is17bits. The total harmonic distortion (THD) is smallerthan-110dB which satisfies the demand of the design and makes margin for therealization on circuit-level.The sigma-delta modulator is realized by switched capacitor circuit on circuit-level.It should be paid more attention to the design of the first integrator which can affect theperformance of the modulator greatly. The chopper stabilization is adopted to remove1/f noise of the modulator. The comparer uses the dynamic latch architecture controlledby a clock signal which can decrease the power dissipation of the quantizer. Theswitched-capacitor common-mode feedback is used in full differential operationalamplifier in the integrator. Meanwhile the design of non-aliasing clock can eliminate theinfluence of non-ideal switches in the modulator such as channel charge injection andclock feed-through. The modulator is designed using standard CMOS0.5-μ mtechnology. After simulating the modulator on circuit-level in Cadence the results showthat the noise floor of the modulator is under-120dB and the ENOB is15bits. The totalharmonic distortion (THD) is smaller than-100dB.