Realization Of Verilog-to-MSVL Program Translation Software

Software emulation has a very important significance in hardware design, it’s theprimary means of logic design, performance analysis and system verification. As one ofthe mainstream description language of simulation tools, Verilog is widely applied indigital electronic systems design. By using it, designers can not only perform logicdesign at different levels, but also do some system simulation, timing analysis and logicsynthesis. However, since the simulation software is subject to high cost andcomplicated application circumstance, it does not apply to general applications, such assystem evaluation, performance analysis and so on.As a kind of Temporal Logic Programming Language, MSVL is based onProjection Temporal Logic. It combines modeling(Modeling), simulation (Simulation)and validation (Verification), also has the advantages of simple simulation environment,low cost, and fast simulation speed, etc. This paper mainly discusses a ProgramTranslation Software that translates the Verilog program to the MSVL program. Firstly,the syntax and semantic of MSVL and Verilog are briefly introduced. After that, theprinciples and realization process of the software are presented in detail. Finally, someexamples are demonstrated to test the functions of the software. The simulation andverification of the MSVL code, wich is successfully translated to, are also conducted bymeans of the interpreter of MSV.The results show that this Verilog-to-MSVL Program Translation Software canconvert Verilog program to MSVL program smoothly, achieving the predetermineddesign goals.