Base On SYSTEM VERILOG-VMM Simulation Environment Designing And Application

Verification becomes the bottleneck of modern millions gates ASIC design because it costs 70 percent efforts of the whole design. Therefor to improve the efficiency and quality of verication is an urgent affair for modern IC design. Based on the VMM ( Verification Methodology Manual, VMM ) part of SystemVerilog language and the VCS simulation tool, a new method for module-level verifications is introduced for the RTL design with Verilog HDL language. This method which is applied to the functional verifications for digital logical module absorbs random test means and so on to assure the completeness and correctness of verifications.According to the comparison of severial mainstream verification languages, the feature and advantege of System Verilog verification language is introduced particularly. And the VMM methodlogy and validation framework are discussed in detail.Furthermore,from the perspective of an ASIC verification engineer, the whole module verication for chip is highlighted. And some notices are given according to the detail introduction of each verification flows.The simulation and verification environment based on SystemVerilog-VMM is proposed referring to the classical architecture of SystemVerilog-VMM . Following the verification flow, the CPURTX, CPU interface module is verified. The verification flow is stressed including the analysis of test point, the design of verification scheme, the set up and debug of verification environment. Meanwhile, the reusability and scalability of the verification environment is discussed in detail.