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Research Of Moire Fringe Nano-scale Subdivision Based On CMOS

Posted on:2015-06-13Degree:MasterType:Thesis
Country:ChinaCandidate:J M YangFull Text:PDF
GTID:2298330431494518Subject:Detection Technology and Automation
Abstract/Summary:PDF Full Text Request
Nano-scale displacement measurement technology has an important position in the fieldof precision displacement measurement, which is the prerequisite for solving manyhigh-resolution and high-precision questions in the future. Among them, the displacementmeasurement of grating has such advantages as good reliability and high precision, practicalnano-scale grating displacement measurem ent sensor developed with a large range, highaccuracy, low cost and other properties have important significance in the displacementmeasurement.Grating displacement measuring system based on the moiré fringe theory, theimprovement of moiré fringe subdivision accuracy occupies an important position in thegrating displacement measurement system, which is determined by the resolution and errors ofalgorithm. To obtain moiré fringe with higher resolution, CMOS is used to obtain the moiréfringe signal in this paper, the resolution is mainly restricted by the pixel size, the smaller pixelsize, the greater number of pixels within one stripe period, the higher resolution. Algorithmcan be considered from two aspects, that is amplitude and phase. For CMOS output moiréfringe signal has better periodicity, if the relative displacement of moiré fringe is obtained bymeasuring the change of amplitude from a point, it is not conducive to the error average ofdata processing, therefore, the article focus on the phase, to obtain the relative displacement ofthe grating by calculating the phase difference between the moiré fringe of two times.Correcting MPFFT algorithm is used in the phase measurement algorithm. The spectrumleakage is inhibited to some extent by using MPFFT, it can also reduce the phase measurementerror caused by frequency offset and improve the phase measuring accuracy comparing withconventional FFT.DLIS2K linear CMOS sensor is chosen in this project, its pixel size is4μm, driving andconfiguring signals required for DLIS2K are all generated by FPGA, correcting MPFFTalgorithm is implemented by FPGA devices, the integrated simulation of Quartus II shows thisalgorithm is effectiveness, the result is consistent with MATLAB.When the pitch is20μm and two grating angle is about0.56°, it can achieve512segments of fringe period. The corresponding displacement resolution is about0.04μm. In the different situation of frequency offset and phases, the maximum phase measurement error ofcorrecting MPFFT algorithm is less than0.3°, corresponding to the grating displacementmeasurement error is less than15nm, this algorithm can output phase value when the latencytime is3267clock cycles. When the clock frequency is100MHz, to achieve displacementmeasurement, FPGA requires approximately33μs. Under the premise of nano-scalemeasurement accuracy, improves the tracking speed of the system, has an importantsignificance in the field of grating displacement measurement.
Keywords/Search Tags:Moiré fringe subdivision, CMOS, Correcting MPFFT, FPGA
PDF Full Text Request
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