Design And Implementation Of FPGA-based Image Boundary Detection System

Techniques of image boundary detection are widely used in computer vision applications,including image segmentation, object recognition and classification, etc. Boundary detectionusually requires some basic information concerning calculation of color, gray scale, texture,etc, and the process of which requires a lot of complicated calculation. Due to the demand ofhigh speed and heavy computation in image boundary detection, traditional processers basedon serial instructions can hardly implement the real-time computing of high-quality imageboundary detection. With the development of the Internet of Things, boundary detection willfind more applications in embedded systems with computing time limited. Thus, to acceleratethe computation for better real-time performance is a big issue to deploy high qualityboundary detection techniques in real world applications.Parallelism is a feasible way to solve the problem mentioned above. The disadvantage ofthe GPU-based boundary detection computation is higher power consumption although it hasbetter productivity. For instance, the power consumption of NVidia GTX480is over200Watts at work. Because power consumption is one of the key factors affecting embeddedsystems, other techniques to accelerate boundary detection computation with lower powerconsumption should be considered.FPGA, as programmable logic device expert in supporting different types of fine-grainedparallelisms, is potential to provide high computational speed with higher energy efficiencyand lower power. This paper proposed and implemented a FPGA-based parallel imageboundary detection system in order to deal with weak real-time performance of high-qualityboundary detection algorithm processing. In this paper, a high-quality image boundarydetection algorithm-Pb (probability boundary) probability boundary detection algorithm isselected for the study, and algorithm flowchart is presented in detail. Firstly, the parallelism ofPb algorithm is analyzed. The main ways of parallel computing are task parallelism, dataparallelism and pipelining, which provide a reference for hardware circuit design of Pbalgorithm. Then, based on analysis of parallelism, part of the algorithm is optimized to makeit more suitable for the design of hardware implementation and the complex part of algorithmis realized in a parallel way to reduce the computation time. Meanwhile the balance betweenthe hardware resources and processing speed of FPGA design is considered, in order to makesure the system achieves the best overall performance.Through optimizing design, Pb boundary detection system is implemented in a XilinxVC707board of XC7VX485T-2FFG1761C. This system is able to process481*321images atthe frame rate39fps, when the working frequency is200MHz. It provides a solid foundationto demploy Pb in real-world applications.