Font Size: a A A

An All-Digital Phase Tracking And Locking Mechanism With Dynamic Element Matching And Low-Power Phase Detecting Technology

Posted on:2014-04-15Degree:MasterType:Thesis
Country:ChinaCandidate:P F LiuFull Text:PDF
GTID:2298330434972467Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
PLL (Phase Locked Loop) circuit is widely applied in wireless-communication chips and clock recovery chips.Because the traditional PLL circuits are usually full-custom designs (belong to the analog/RF integrated circuits), its performances are badly influenced by PVT (Process Voltage Temperature) conditions. On the other hand, digital ICs remarkably benefit from the progress of the nano-meter fabrication semi-conductor process while analg/RF ICs do not, because the passive devices in analg/RF circuits(e.g. capacitance,inductance) can not scale down.Under this circumstance, a new digital-design-methodology-based ADPLL was invented, this ADPLL can be hardly influenced by the fabrication process, and can be easily integrated with other digital circuits to make smaller chip area.This type of ADPLL can also benefit from progress of digital processes, so, in a word, the application of ADPLL will beome more popular along with the development of IC process.First of all, this paper illustrates and analyzes the traditional architecture of ADPLL and put forward several problems on this architecture, base on this, dynamic element matching and low-power phase detecting technology applied in all digital Phase Lock Loop are proposed. The lower-power phase detecting lowers the power consumption and circuit complexity in digital circuit by simplifying the traditional phase detecting principle and developing a new-type phase detector. Meanwhile, in order to weaken the influence of digital controlled oscillator (DCO) capacitor mismatch to loop output tuning curve, the dynamic element matching technology is applied in the all digital Phase Lock Loop.The proposed Phase Lock Loop is fabricated in TSMC0.13um CMOS technology. Simulation results show that the low-power phase detector works correctly, cuts the power consumption by46.8%, and saves33.5%area; also, the locking range of the proposed Phase Lock Loop is from2.4GHz to5.2GHz. The measurement results show that the tuning curve of DCO with DEM is far closer to the ideal tuning curve than the DCO without DEM.
Keywords/Search Tags:all digital Phase Lock Loop, digital phase detector, low-power, dynamicelement matching, tuning curve optimizing
PDF Full Text Request
Related items