Design And Implementation Of On-chip Memory Module In Real-time FRC System

In recent years, people’s subjective demands on high-quality visualenjoyment and the objective development of semiconductor technology bothstimulated the flourishing of UHD TV industry. But because of the bandwidth limit in transmission system,UHD TV programs are often transmitedin a low frame rate.Meanwhile,refresh rate of display devices with largescreen has remarkably increased and videos’ frame rate is lower than thatrefresh rate.This mismatch directly invited smear,pause,fuzzy and bad visualeffect.As one of the main video post-processing methods,frame rateconversion can increase videos’ frame rate in an efficient way and finallyoptimize images’ subjective quality on high-refresh-rate screens.This papermainly designed and implemented the core module in FRC system——Memory Module on Chip.In FRC system,it’s a core issue to decrease the amount of off-chipvisits.In the system implemented in this paper,we mainly use the MemoryModule on Chip to lower off-chip visits and meet UHD videos’ demands ondata.This paper started from requirements in throughput and clockcycles,dividing different reqrested pixel blocks into multiplesequences,designing corresponding optimized RAM array and developingmapping among video sources,off-chip devices and on-chip memory.Thenthis paper presented the whole designing plan for the Memory Module onChip,which met all demands on data and band width.Also,dataupdating,reqrests control and post-processing of data,the three main sectionsalong reading and writing chanels in the design were discussed in details. To promote the system’s performance,this paper made furtheroptimization and the focus was on timing,throughput and area.In the aspectof timing and throught optimization,new hand-shaking protocol andpipe-line were designed in order to save clock cycles and increasethroughput respectively.By unifying ths storage format for8bit and10bitvideo sources,lots of circuits were resued and system area decreased.At thesame time,new visiting strategy towards SDRAM was designed to make thevisiting process more efficient.Last but not the least,this paper talked about the synthesization andverification part,delivering verification plans in details and testing all-roundfunctions of the Memory Module on Chip from module level and systemlevel.All results shows,the design in this paper meets the300MHz frequencyrequirement and in65nm CMOS technology,this module takes226,710gates and7.86mm2in area.