| As a basic link of image processing, image denoising is the essential procedure to improve image quality and acquire more details, especially more and more significant when multimedia communications widely employed. Numerous image denoising algorithms are intensely studied, especially block-matching and3-D filtering algorithm (BM3D) included, and an embedded system on FPGA is designed completely based on SOPC technology to accomplish getting, denoising and storing images in this thesis.The out-standing result is achieved by BM3D algorithm, which combines local with non-local means effectively. The algorithm is complicated and processing speed is so low as a result of procedures such as block-matching and3-d transform caching large amounts of data. Two revised methods, semi-local means and judging block matching directions means based on BM3D, are proposed to increase efficiency on the premise of excellent denoising result, thus laying the foundation of hardware implementation on FPGA.Implementation of revised algorithms in embedded system on FPGA is designed emphatically based on SOPC technology in this thesis. SOPC Builder tool is used to complete structuring Nios II processor system with peripherals such as on-chip memory and SDRAM connected together by Avalon bus for the whole system. Core image denoising algorithms are completed by Nios II processor and SPI is controlled to read original images from SD card and write images to SD card after final denoising process. From all the run result we can reach our conclusion that the hardware system has the effect of image denoising as well as algorithms simulation.Relative to current state that most of image denoising algorithms are just simulated in high-level programming languages, not only are two revised BM3D algorithms proposed in this thesis, but also the project in the thesis provides a practical proposal for implementation of an image denoising embedded system on FPGA, which confirms to the hot research area of image processing system based on soft-core processor and implements the revise BM3D algorithms on embedded system conveniently and flexibly. |