Hardware Implementation Of μC/OS-Ⅱ Communication Mechanism Based On FPGA

Because RTOS has very significant features, such as real-time scheduling,determined response time and reliable system, it has already been playing adecisive role in many fields, such as industrial control, automotive electronics oraerospace. A fly in the ointment is that, nowadays existing RTOS kernel wassimply as an attachment in software applications. So RTOS has brought a seriesof problems, for instance the increasing storage space costs, heavy applicationload etc. Especially in some situation that requires very strict on real-time, cannotreach the requirement.In order to solve the problem that the RTOS kernel leads to decrease theexecutable of applications, the solution is to design the scheme to realize ofRTOS harden based on FPGA. It means that RTOS kernel is hardened to FPGAplatform, makes it as an independent module from processor, and can execute inparallel. The general framework of RTOS is composed of I/O registers, interruptcontroller and the main function modules of RTOS. The hardware implementationprocess is that the parameters are sent to the input register of the specifiedhardware circuit through the data bus, and the hardware logic circuit process, theresult will be sent to the output register for CPU to read finally.The research object of the thesis is μC/OS-II, according to the parallelhardware logic circuit characteristic; the data structure of the existing softwareμC/OS-II should be modified to build the various functional modules forhardware logic structure first. The entire design was described by the VHDLhardware language, meanwhile, the accuracy of this design has confirmed by thesimulation of the ISE8.2software.In the paper, the first thing to do is understanding and analyzing theμC/OS-II in depth, then design the overall framework of the μC/OS-II hardened,it includes the overall design of hard core and the overall design of software interface. The focus is to design and implement the synchronization andcommunication mechanisms of harden μC/OS-II, the synchronization andcommunication mechanisms contain semaphore management module andmailbox management module. The function will be described and realized byVHDL, then simulation and verification further. The result shows that hardeningthe synchronization and communication mechanisms can reduce the cost ofsystem and improve the real-time.