The Optimal Power Network Design Of An NSE Chip

As the rapidly development of integrated circuit in the recent thirty years, the technology node is decreasing followed by Moore’s Law. In the deep sub-micron integrated circuit design, the challenge of physical design is not only a large number of transistors, but also the challenge of power, speed and area. With the decreasing technology node, especially, the power metal wires are more and more narrow, which leads to the challenge of power constraints.A design of network search engine based on CAM has been done in this paper, which includes the whole back-end flow from logic synthesis to signoff verification by SMIC130nm technology. The core voltage is1.2V and the10voltage is1.5V, operating frequency is300MHz, the area is273mm2. The main challenge is the8-layer full-custom IP of CAM, the big IP leads to a high challenge of power, timing and area constraints.In this paper, we mainly describe the optimal design of power plan and floorplan in this design. The design has been optimized by increasing the local density of power straps in huge-power area, and changing the local routing guide, assisted by multi-layer overlap power ring with routing resource rational utilization and Multi-corner-multi-mode timing met. In the optimal design, the IR drop of power network has decreased65%, maximum current density decreased87.7%, and the ground bounce of ground network has decreased35%, maximum current density decreased66.3%, and MTTF increased more than ten times. The optimal design has completed the power constraint and met the power signoff standard. This optimization of power plan is reference for the power challenge design.