IR Drop Analysis And Optimization Of 40nm Switch Chip

Nowadays,human beings have stepped into the era of big data,and the performance of mobile communication devices has been continuously improved.As a digital chip that supports multiple protocol types,switching chips were widely used in data collection,data storage,and external communications.Since the switch chips need to have the characteristics of high bandwidth,low latency,low power consumption,and high reliability.However,as the main frequency of the chip increases,the logic complexity inside the chip has increased significantly,and the power consumption of the chip has become larger and larger,which makes it easier to cause excessive voltage drop(IR Drop)inside the chip.If the power supply of the internal logic unit of the chip is insufficient,it will increase the delay of the interconnection line,thereby reducing the performance of the chip.Even more seriously it will cause the functional error of the chip.Therefore,how to optimize the chip voltage drop will become a difficult problem in the back-end physical realization process.Based on a switch chip under a 40 nm process,this paper deeply discussed the optimization method of static and dynamic voltage drop in the back-end physical realization process.First of all,the composition of the power consumption of the digital circuit was analyzed,then the common optimization strategies of voltage drop in the back-end design are explained.In the chip top-level layout planning stage,the layout planning of each sub-module was completed and the Bump placement and power network planning at the top of the switching chip were physically implemented.When placing and routing the sub-modules,combining utilization rate,congestion estimation,and timing estimation,the placement and winding of standard cells are completed.According to the layout and routing results,the placement density of standard cells and input and output buffers inside the sub-modules was optimized,the number of power supplies in the macro cell and the channel between them was increased.Secondly,the process script of the RedHawk simulation tool for voltage drop analysis was designed.The design data file and GSR file in the process were analyzed and explained.Finally,after completing the static and dynamic voltage drop optimization of the chip,the package parameter extraction process was achieved.The package parameter model of the Flip-Chip was extracted using the RedHawk-CPA tool,and the static and dynamic voltage drop results of the switch chip after the package model added were verified.According to the analysis results of the voltage drop after the package layout,it revealed that the worst static voltage drop on the switching chip power supply network was 12.87 mV,which was only 1.17% of the chip working voltage.The worst voltage drop in the example unit was 17.95 mV,which was only 1.63% of the chip's working voltage.The worst dynamic voltage drop on the power supply network was 78.3 mV,which was only7.11% of the chip's working voltage.The worst voltage drop of the example unit was117.78 mV,which was also only 10.71% of the chip's working voltage.Without affecting the function of the switching chip and timing closure,the worst voltage drop value in the chip was effectively reduced,so that the voltage drop results meet the design sign-off goal.This research provides a practical reference for the chip back-end designer.