Research On Hardware Acceleration For Elliptic Curve Cryptography

Elliptic curve cryptosystem (ECC), which was independently proposed by Neal Koblitz and Victor Miller, is a kind of public key cryptosystems. Public key cryptosystem, also named as asymmetric cryptosystem, was first proposed by Diffie and Hellman. Compared with the traditional private key cryptosystem which uses the same key to encrypt and decrypt, it is based on the intractability of math problems and uses different encryption and decryption key to encrypt and decrypt, respectively. The emergence of public key cryptosystem effectively solves the problems of key distribution and key management which exist in the traditional cryptosystem. Compared to other public key cryptosystems (such as RSA), in order to provide the same level of security, ECC needs less computation and has a shorter key length, which makes ECC the ideal public key cryptosystem for applications with limited resources.ECC can be implemented with either software or hardware. Software implementation can be realized by using an advanced programming language on general purpose processors, which has the advantage of low cost and short development period. However, its low execution efficiency may not satisfy the strict performance requirements for certain applications. Hardware implementation refers to designing hardware modules or chips to implement ECC. In spite of the high development cost and long development period, hardware chips’ execution efficiency overcomes the weakness of performance in software implementation. In addition, when implementing in hardware, all the operations processed internally and physically isolated, thereby it has a higher security and reliability.In this thesis, we propose two hardware acceleration schemes based on FPGA and ASIP to accelerate the execution speed of the ECC algorithm.Hardware acceleration scheme based on FPGA refers to selecting the appropriate algorithm according to the hardware features of FPGA, and improving the algorithm to make the most of the highly parallel of FPGA, meanwhile minimizing the consumption of hardware resource, and designing the better modules corresponding to the operations included in the algorithm. This scheme reduces the idle cycle of the main module by adjusting the logical relationship of each module and using the parallel processing and pipelining techniques. Therefore, it achieves the high performance with limited hardware resources.Hardware acceleration scheme based on ASIP refers to designing user’s special instructions and building processor’s high-level model by LISA according to the existing processor and instruction set architecture, as well as simulating and verifying the high-level instruction set for the processor model. We then transform the model built by LISA to the model described by Verilog/VHDL in RTL level, and use synthesis tools to synthesize and place/route the model described in RTL level. Finally, we transform the processor model to the gate-level circuit and verifying the correctness of the model.