Implementation Of Channelization And Digital Beamforming Of Wideband Radar On FPGA

Wideband radar with large signal bandwidth has advantages in distance resolution, anti-jamming and target detection. It has gained widespread concerns around the world. Very large scale integrated circuits(VLSI)reduce the volume of radar systems and improve the performance of radar signal processing effectively. For the requirement of great amount of transmission and calculation for wideband radar, the engineeing application of the channelized digital receivers and the wideband digital beamformer based on FPGA is studied. The main results obtained are shown below:1. The modular design of the channelized receiver based on FPGA is studied. Based on the analysis and the comparison of different implementation structures for the digital down conversion and the channelization, certain FPGA modules are designed. The principle of the exchange between area and speed are used, which improves the working stability of FPGA and saves the resources of it as well.2. The multi-channel high-speed data transmission is studied. A multi-channel high-speed data synchronous transmission method is proposed, which has less links and lower design complexity. To solve the time delay problems, a synchronous transmission measurement system is desigend. Ths application of IODELAYE ensures high precision of the measurement, a long with the MMCM makes the system have a wide measurement range.3. The algorithms of wideband digital beamforming are studied. A new wideband digital beamforming algorithm is presented based on the random delay filters. The CVX toolbox is used to design the random delay filters, showing a good performance in the passband with sufficient flatness and large bandwidth. Simulation results show that the time delay of each sensor can be compensated accurately.4. The hardware design of wideband digital beamforming is studied. For the requirements on the large amount of data transmission and caluaulation for wideband digital beamforming, a high-speed multi-channel wideband digital beamformer(DBF) with 5 FPGA is designed. The high serial interface and the parallel calculation of FPGAlead to high speed data communications, strong computing ability and easy integration. The modular design of wideband digital beamforming on the platform is completed. As an elementary investigation, the design shows a good performance.5. The high-speed data transmission on the optical fiber is studied. The hardware design of the optical fiber communication(OFC) base on FPGA is introduced. For the requirement of OFC, a flexible and efficient customized transport protocol is designed, whose peroformance is tested as well. The transmission process of JESD204 B protocol is analysed which use the JESD204 B IP core to complete data transmission. The Xilinx Integrated Bit Error Ratio Tester(IBERT) for the high-speed interfaces is introduced.6. The AXI4 protocol is studied. For the requirement of efficient communication between the FPGA modules, the operating modes and principles of the AXI4 protocol are introduced. Using the AXI4-Lite and AXI4-Stream interface respectively, the data communication between IP cores are realized.7. The simulation and testing methods for FPGA’s are studied. A simulation platform is designed. The Verilog system task functions are used to read the test vectors generated by Matlab and output results, improving the simulation efficiency greatly. For the requirement of FPGA testing on power, two common test methods are introduced. A software testing method for real-time observation of large amounts of data is designed. Finally, the integrity of the verifications of simulations and tests are analyzed.