Research And Implementation Of Rateless Codes On Physical Layer

Fountain codes change the recognition about traditional channel codes with fixed code rate.The transmitter stop sending encoded symbols until the receiver can decode them correctly. Nowadays, Rateless codes have been applied in noisy channel. Research on the design and implementation of Rateless codes are still important for noisy channel.Firstly, we present current status of digit fountain code research and common fountain codes transmitted over erasure channel. Then we focus on the introduction to the principles of encoding and decoding algorithm of Kite codes, which is designed for AWGN channel. To reduce the complexity of implementation on FPGA, we proposed a kind of code construction algorithm for simi-random Kite.Secondly, we constructed the SR-Kite with information length of 1024, we choose the proper parameters for codes. The decoding algorithm is chosen after making the comparison with decoding results applied in different decoding algorithms. For the view of the implementation, we decide the proper the quantization scheme and parameters of decoding in the implementation of decoder on FPGA.Thirdly, for the characteristic of double diagonal SR-Kite check matrix,a single-recursion pipeline method is introduced as encoding algorithm. We applied a partially-parallel architecture is designed to store the middle results, which helps increase the encoding speed of encoder. Meanwhile, the result of FPGA logic synthesis and timing simulation verifies the correctness of the SR-Kite encoder.Finally, according to the parity-check matrix do not process the circular or quasi-cyclic structure feature, we design the decoder structure based on layered decoding. We also propose a permutation method to make the SR-Kite check matrix suitable for layer decoding. The result of FPGA logic synthesis and timing simulation verifies the correctness of the SR-Kite decoder.