FPGA-based Design And Implementation Of High-speed And High-density Storage System

With the rapid development of the information age, information exchange, forwarding and storage between and inner different complexes has become more and more indispensable to build the foundation of the information era. Data storage technology has become an important area to bring the revolution of thescience and technology. In recent years, data storage as an important part of theradar signal processing system, its data rate, storage capacity, power consumption, the maintenance of the complex work environment and other performance parameters have been increasingly improved. The main content of this article is to find a measure of designing the storage device, which could meet all the needded aspects metioned above.Micron’s MLC Flash memory chip selected as the storage medium, each read and write speed can reach dozens MB / s, is interalintegrated multiple independent operating units. With these features, multi-level Pipelining, multi-chip parallel operationis an effective way to improve data access rate, meet the minimum design speed of 1.5GB / s.Xilinx’s Virtex-6 family of chips is chosen as the control device,in charge of achieving the main logic of the circuit board. Xilinx Inc.,along with Altera Corporation as one of the global two largest FPGA’s manufacturers, can provide users with a huge variety of chip products,whitch have a wealth of experience and consumers.Due to highly configurable structure, the embedded processor built with Microblaze softcore, shortens the product developing cycle and ease to modify.The entire design process could be completed using EDK and SDK development environment provided by Xilinx.PCI-E, Serial Rapid IO and other high-speed interfaces are designed By Verilog HDL.High-speed interfaces inner Virtex-6 chips are GTX hardware-based, can achieve physical layer and data link layer’sstandard interfaces of different protocols by using different IP cores.Then introduces PCI-E Bus Protocol, analying the working process of the transaction layer, and completes the PIO and DMA transfer mode by assemblingand de assembling packages.It studies the data verification mechanism of Error Detection and Correction, introduces the theoretical principle of the BCH code and the derivation of data encoding and decodingalgorithm. By optimizing the design methods, choose the measure of matrix multiplication to achieve BCH coding part,BM Iterative Algorithm and Chien Searching Algorithm to BCH decoding parts.The paper is meant to discuss a design and implementation method of high-speed and high-density storage system, based on a laboratory project of a radar signal processing system according to the limitation of the radar system requirements and workingconditions. With NAND Flash as the compose of storage array, Xilinx’s Virtex-6 family FPGA as the mastercontroller, the high-speed and high-density storage system has achieved a literacy rate of not less than 1.5GB / s, huge capacity of 3TB, PCI-E and Serial Rapid IO high-speed interface, error control coding with certern error correcting capability. The system six basic operations: record, playback, import, export, erase, and coercive stop.In accordance with massive experiments, the results obtained show that the high-speed and high-density storage system has meet the design requirements of working uninterrupted, stabilized and good maintainability in harsh environments.