The Test Solution On The ATE To Repair The Embedded Memory

Now, semiconductor integrated technology has been widely used in the latest electronic equipment and the embedded memory occupies the absolute status in the chip. The proportion of occupied chip area is growing, but also for a more prominent role in the chip. It has become a significant feature of the chip development. However, due to its complicated structure and high density technology, we will find many chips do not pass in wafer testing process. The reason lies in the malfunction of the embedded memory. As a result, the wafer yield is low. It has become an important factor to affect the chip yield, but the low yield is not allowed in the production. In order to improve the whole wafer yield and improve the reliability of embedded memory, it is very important and urgent to repair the faulty embedded memory in the process of testing. It will have great market application value and therefore worthy of further study.Firstly, the paper introduces the background and the current development of embedded memory fault repair. Starting from the fault type and algorithm analysis of embedded memory which leads to the three basic methods of embedded memory test, embedded memory built- in-self-test is studied. On the basis of embedded memory built- in-self-test, the paper makes algorithm analysis of the fault and then introduces the traditional repair technology. In view of the problem that costs too much chip size in the traditional repair technology, specific optimization method for traditional repair technique is put forward. Then do a thorough analysis of specific optimization process and focus on the basic part and implementation process of a new repair technology. The paper designs seven main test modules based on this new form of repair technology and further stud ies the specific design idea and design method of the various modules; In addition, in order to reduce test time in the process and save more test cost for enterprise, this paper explains the basis of the optimization and the method based on the fuse module which is one of the seven test modules and innovatively puts forward three kinds of improvement ways to optimize the process code. It can reduce the test time of this process greatly and finally gives the solution of whole test process for the embedded memory repair. In the end, on the basis of the above modules design, I build the overall testing process in the ATE test platform. By debugging and optimization of test program, I make actual online test of the wafer. After analyzing and summarizing the test results generated by the system, we can find that, through the process of embedded memory repair, 42 chips in a wafer are repaired. That directly makes the chip yield increase from 55.98% to 59.54% and the yield is increased by 3.56%. It can reduce the loss of the chips to achieve the desired goal and also verify the correctness and feasibility of the whole test process solutions; In addition, for the time-optimized test process, fuse module can save almost half of the test time. The test time of this module in a wafer is reduced by 189.701 s to 94.752 s and average test time of each chip in this module is reduced by 160.848 ms to 80.362 ms. This result can also verify the accuracy of three kinds of optimization process code. As a whole, the test results show the overall test process solution has realized improvement of wafer yield and reduction in test time. This solutio n is effective and provides the technical support for the development of embedded memory repair. It will have broad application prospects.