Research On Embedded Memory DFT And On-chip Repair Technique

With the rapid development of semiconductor integration technology and wideapplication of SoC, embedded memory is becoming more and more substantial.However，the highly compact memory structure and complex manufacturing processintroduce chances of physical defects in the memory, which is becoming a key factor toaffect the yield of chips. Therefore, the study of effective memory testing and on-chiprepair methodology has become significantly important.In this thesis, the research status of embedded memory test and repair technologyis discussed. In order to solve the low efficient problem of traditional test and repairtechnology, a16K×16bit SRAM built-in self test (BIST) circuit based on March16Nalgorithm and its top level connection circuitry are designed, by analyzingdesign-for-testability method. And an E-fuse based embedded memory on-chip repairsystem is built, which uses redundancy registers to take place of the faulty memorycells. The BIST circuit is simulated with the Modelsim tool, and the correctness of thecircuit functions is verified. The repair circuit is simulated and back-end designed, theresults show that the system can achieve memory troubleshooting, and the circuit areaincreased is less than10%of the original memory area, which achieves the desiredfunctionality. On the base of the above studies, the repair system is optimized for theSoC with a huge number of memories built within a single chip, which further reducesthe area of repair logic. It provides technical support for the development of embeddedmemory test and repair technology.