Design And Research Of Digital Decimation Filter For Sigma-delta ADC

In recent years, integrated circuits(ICs) and Digital signal processing(DSP) technology develop rapidly. So ADCs(Analog to Digital Converter, ADC) as indispensable interface circuit between the Analog system and the outside world, have been paid more and more attention. They are gradually becoming the focus of the main promotion and development in the wireless communications and other industries. Based on oversampling and noise shaping technology, Sigma-delta ADCs have a higher accuracy and a higher SNR, which have been widely used in many fields of integrated circuits. Sigma-delta ADC is composed of Sigma-delta modulator and digital decimation filter. Sigma-delta modulator determines the conversion accuracy of the entire Sigma-delta ADC system, and the digital decimation filter determines the power and area of the system. In order to reduce the size and power consumption of the whole system, designing a low area, low power, highly integrated digital decimation filter is very necessary in the Sigma-delta ADC circuits. The author’s major contributions are outlined as follows:1. The basic principle and structure of Sigma-delta ADCs are studied. Firstly, the basic principle of ADC is introduced. And then, we focus on the principle, implement structure, performance parameters and key technologies of Sigma-delta ADCs.2. The principle, structure, performance simulation and analysis of Sigma-delta modulator are studied. This paper presented a four orders single-loop single-bit CIFB(Cascade- of- Integrator- Feed- Back) Sigma delta modulator, determined parameters of the modulator according to the requirements of the design in the article, and modeled and simulated the structure by using MATLAB. With a clock rate of 81.92 MHz and an oversampling ratio of 128, the modulator achieved a 116.9d B signal-to-noise ratio and 19.3 bits accuracy. The simulation results show that the Sigma-delta modulator designed has a good noise shaping effect.3. The basic principle and structure of Digital decimation filter(decimator)were studied and designed. The principle and structure of decimators were studied firstly inthis paper. And then based on the analysis of the principle, a decimator was designed. Designed in cascaded structure, the decimator was divided into three levels. The first level was CIC decimation filter, which was used to implement the main function of decimation. The second level was CIC compensation filter, which was used to compensate the pass-band attenuation of CIC decimation filter, and realize 2 times of decimation. The third level was half band filter, which was used to adjust the stop-band attenuation and transition zone width of the whole system, and realize double decimation to the useful signal.4. The decimator designed in this paper was simulated by using simulink in matlab software. Firstly, the performance parameters of the digital decimation filter was defined according to the requirements of the whole system and the Sigma-delta modulator, such as input frequency of 81.92 MHz, the output frequency of 640 k Hz, decimation ratio of 128. And then, the Simulink tool is used to build the model of the digital decimation filter and perform the simulation. The simulation results show that the decimator designed has a good performance.5. The hardware implementation of the decimator was studied in this paper. The codes of the decimator were given in Verilog HDL, and the function of the system was simulated by Modelsim. The sampling rate after filtered by the decimator became Nyquist rate. And then, it is synthesized with EDA tools, and the gate-level netlist is obtained. Static timing analysis indicates that it meets the timing requirement. Finally, the layout of the decimator was completed by using Encounter.