Design And Research Of Digital Decimation Filter For 24 Bit Sigma-delta ADC

This paper is the design and research in a digital decimation filter in of a 24 bits Sigma-delta ADC.We designed a decimator which could deal with a 256 MHz input signal and give out a 1MHz output through ASIC digital methodology starting from the research of the Sigma-delta modulator' s structure.The major parts of this paper and author's major contributions are outlined as follows:1.The basic principle and structure of Sigma-delta ADC.Firstly we make a brief introduction to the principle and structure of ADC, then we focus on the principle, implementation structure, key technology and performance parameters of Sigma-delta ADC.2.Basic principle and structure of Sigma-delta ADC and its performance simulation analysis in Matlab. According to the whole system requirements, we build a four stage single ring CIFB Sigma-delta modulator and simulate its system performance.We could get a 1MHz output when given a 256 MHz input.The signal noise rate of this modulator achieved 123.5d B which equals to an accuracy of 20.22 bit.3.The basic principle and structure of decimation filters.The principle and structure of decimators were studied firstly in this part.Then we come up with a three stage modulator, the first stage is a CIC filter that could achieve the 32 down_sampling, the second stage is a CIC filter to compensate for the decreasing in the CIC decimation filter's passband.The last stage is composed of two half band filters.This stage could achieve four times of decimation, adjust the stop-band attenuation and transition zone width of the whole system.4.The system design and simulation of decimator.We defined the performance parameters of the digital decimation filter according to the requirements.The frequency of the input is 256 MHz while the output is 1MHz, that is to say a decimation rate of 256.Then we build the three stage respectively and perform the simulation.5.The ASIC impentation of the decimator.We wrote the RTL code and testbench of the decimator, then we performed the functional simulation in Modelsim.After this the RTL code is transferred into the gate level netlist in the desing complier.During the synthesis we checked the setup timing report to make sure it is met.Then we throw the netlist into ICC to do the physical implentation, which is composed of Floorplan, Placement, CTS and Route.At last we did the signoff static timing analysis in Prime Time with the parasitic parameters extracted by starrc.When this is done we added the DFM setting and saved the layout of decimator.At last we performed the DRC and LVS check for the layout in Calibre, the result showed no violations.The research in this paper has a certain significance for the design of the down-sampling digital filter in high precisive Sigma-delta ADC.