Study And Implementation Of High-Performance Delta-Sigma ADC Based On Tracking Quantizer

With the rapid modernlization of information technology and the popularity of handsets, demands for low-power, high-speed, highly accurate information processing devices keep increasing. The Delta-Sigma ADC, with its high resolution and low cost, is widely applied in mobile communication. However, due to its limited speed, the Delta-Sigma ADC is facing a bottleneck in its development. Thus, improving the speed of Delta-Sigma ADC has become a research hotspot.Based on the traditional feedforward topology of multi-bit quantization Delta-Sigma ADC, this thesis proposes a tracking-quantizer based architecture. The tracking quantizer restores current input in the digital domain by integration. It only quantifies the residue of current input and last input, which reduces the input swing of quantizer effectively compared traditional quantizer. Therefore, it lowers the number of comparisons and power consumption, and improves the conversion rate. With the adopted feedforward architecture, the integrator only needs to deal with quantization noise, which reduces the signal swing of integral loop greatly. The quantization noise can be further supressed by increasing the quantization bit to8bits, lowering the design requirement of operational amplifier and power consumption. The data weighted average (DWA) technique used in feedback loop reduces the nonlinearity caused by multi-bit quantization, which protects the signal to noise ratio distortion (SNDR) of the system. System architecture is determined by mathematical calculations as well as modeling and simulation in Matlab, with a summarization of design methodology. Varieties of non-ideal factors in an actual circuit, such as finite operational amplifier bandwidth, slew rate and DC gain, etc., are modeled and simulated in the system to provide evidence in practice.The DAC in the8-bit tracking ADC adopts monotonic switch structure, which not only saves50%capacitance but also reduces power consumption significantly. The dissertation presents an improved topology for traditional double-tail structure comparator, which has lower offset voltage, lower noise and only requires single-phase clock for control. Therefore, the improved comparator also relaxed the requirement for clock generation circuits. The sampling switch with bootstrap technique improves the linearity of sampling switch and increases the tolerance of input signal swing at0.6V simultaneously. The traditional bootstrap switch circuit is optimized by replacing NMOS transistor with PMOS transistor, which avoids the high-power large-area issue caused by the charge voltage doubler of capacitive structure.The proto-type was fabricated under0.13μm1P8M standard CMOS technology. At a0.6-V supply and50kHz bandwidth with an oversampling ratio (OSR) of16, the Delta-Sigma ADC achieves an SNDR of76.8dB and consumes152.2μW, resulting in a figure of merit (FoM) of0.29pJ/conversion-step. The chip core occupies an active area of only0.25mm2.