In recent years, optical interconnection technology are of attention at high speed, high bandwidth, low crosstalk, and low power consumption advantages, especially in a very short distance optical transmission field.CMOS integrated circuit and CMOS technology platform to promote the silicon photoelectric detector, optical receiving circuit and the development of the integrated optical systems, high speed CMOS high sensitivity of 850 nm wavelength photodetector structure and model to become one of the keys to implement very short distance optical interconnection.So the SOI CMOS compatible with high performance photoelectric detector, and the related technology, manufacturing, has very important practical significance.Based on SOI CMOS technology, the thesis proposed a Resonant Cavity Enhanced(RCE) photoelectric detector structure which can be used in the 850 nm wavelength optoelectronic integrated circuit(OEIC) high speed, high sensitivity and low cost. The technology of photoelectric detector, device structure, and the software simulation research and layout design are implementated. The main research work and innovation points are as follows:1ã€The SOI CMOS structure of resonant cavity enhanced photodetectors is established, and the structure based on 0.5 um processing as carrier of the technology processing. Then the optimized parameters of SOI based photoelectric detectors are given, this structure try to solve the problem between the low quantum efficiency and narrow working bandwidth fundamentally.2ã€The SOI photoelectric conversion mechanism of a photoelectric detector is studied and the carrier characteristics, mathematical model for cavity enhanced photoelectric detector is established. The materials of Si wafer, the DBR mirror reflectivity of resonant cavity and the overall structure are researched and analysised, and implementation scalable property mapping between model and physical structure. Comparing with the results of numerical simulation by MATLAB and processing simulation by TCAD.3 〠Inspection SOI base resonant cavity enhanced(RCE) photodetectors physical size multi-dimensional change influence on its performance, and the "grid active area", "palisade source area" add to the analysis and design of the top DBR mirror structure. The parameters are optimizied to design the optical fiber communication SOI CMOS RCE photodetector.4ã€Design a variety of SOI CMOS RCE photodetector layout structure, including three kind of device size: 30μm*30μm, 40μm*40μm, 50μm*50μm. Two kinds of active area structure: P+ structure of grating type and N+ structure of grid type. Four kinds of distance between active area: 0.8μmã€0.9μmã€1.0μmã€1.1μm, so there are 24 different photoelectric detector structures in total.Through the research of thesis and analysised combination the simulation of TCAD with the simulation of MATLAB, the results show that the correctness of the SOI based CMOS RCE photodetector, and the quantum efficiency increased 100% compared with the ordinary CMOS photodetector. SOI based CMOS RCE photodetector technology compatible with the existing CMOS processing that reduces the production difficulty and cost. In this paper, the research work for the future further research and production of RCE photodetector has accumulated certain experience, through the analysis of RCE photodetector research and development process, lays a foundation for the research and production. |