An Analytical And Optimal Model For Reorder Buffer Size Of Multi-path Routing NoC

Reorder buffer is often needed in multi-path routing NoC to guarantee in-order packet delivery. However, due to lack of worst-case analysis, the reorder buffer size is usually over-dimensioned, lacking worst-case analysis lead to unnecessary area overhead. Based on network calculus, we propose an analytical model and optimal model for worst-case reorder buffer size in multi-path minimal routing NoC, and then implement it with hardware. The main work is as follows:(1) The analytical model of worst-case reorder buffer size in multi-path minimal routing NoC.In traditional method, lacking worst case analysis lead to unnecessary area overhead, we propose an analytical model of reorder buffer. Based on network calculus theory, we establish the equivalent service curve, then derive the upper delay bound of each sub-flow. Further, we establish the reorder buffer analytical model located in the end of the path, at last derive the upper reorder buffer bound of all the sub-flow pairs. Both synthetic pattern and industry case have been utilized for experiments. The results show that compared to worst path, the reorder buffer improvement of optimal path is up to 95.64%, as well as an average of 79.08% when varying contention traffic splitting proportions. An industry case is applied with two kinds of mappings. The results show that worst-case reorder buffer analysis is useful in architecture exploration such as application mapping, with a maximum improvement of 36.50%, which may be considered as one cost in routing/mapping problems.(2) The optimal model of worst-case reorder buffer size in multi-path minimal routing NoC.In order to avoid the time consuming and low efficiency in all-traversing method, we propose an optimal model of the upper reorder buffer bound calculation. First of all, through the selection and forecasting process, we can realize the optimization mechanism, and then we take 4×4 two-dimensional network as an example to expound the optimization process in detail. The experiment results show that with the increasing of contention flows, contention coefficient can better character the upper reorder buffer bound, in the other hand, with the increasing of network scale, the optimization effect is more obvious. For 6×6 network scale, our method increase the calculate efficiency by 52 times and shortened the running time by 269 minutes.(3) The hardware implementation model of worst-case reorder buffer size in multi-path minimal routing NoC.In order to verify the correctness of our analytical model, we realize the hardware implementation model of reorder buffer and then evaluate area and power consumption of reorder buffer. First we give the reorder buffer hardware model realizing by look-up-table, then we give the whole testing mechanism including flow generator, network restructuring by routing node and reorder buffer model. At last we obtain the comparison of analysis and simulation result through experiment, to verify the accuracy of analysis results, at the same time to analyze the reasons of inconsistent trends; we use DC tool of Synopsys company to complete the logic synthesis, choosing 65nm TSMC technology library to evaluate area and power consumption of the reorder buffer model, the results show that area improved 34.1% and power improved 34.1%.