Resrach And Design Of Reorder Buffer Based On-chip Network

As a new communication architecture,Network-on-Chip?NoC?has the characteristics of high parallelism and strong expansibility compared with the traditional bus.Enabling traffic splitting on Network-on-Chip brings multi-path routing function,which significantly increases the link bandwidth.However,due to the imbalance of traffic,the problem of out-of-order data packets is generated,so a reordering mechanism is needed to ensure that the data packets are delivered in order.However,a reorder buffer that is too small may cause packet loss.Therefore,how to minimize the size of the reorder buffer area and ensure that the reordering data packet in the worst case will not be lost has become an important challenge for NoC design.The content of this article is as follows:?1?Study the analysis and optimization methods of 3D on-chip network reorder buffer.Based on Network Calculus,the worst-case reorder buffer model of multiple substreams in the 3D Network-on-Chip is derived based on the reorder buffer of two substreams.A worst-case reordering buffer size calculation method based on traffic splitting is also proposed to reduce the size using the theory of parallel resistance.Experimental results show that,compared with OLITS^[43],the worst-case reordering buffer size has been reduced by 14.4%-20.88%using the proposed method.?2?Propose NoC architecture of multi-level data packet reordering.The traditional data packet reordering method relies on the local single-level packet reordering,which is one of the major causes of on-chip hotspots,thereby exacerbating chip aging issue and even causing interconnect failures.A multi-stage packet reordering?MPR?scheme is proposed,which effectively relieves the hotspots caused by local single-level reordering,thereby improving the thermal security and performance of the Network-on-Chip.The experimental results show that the method in this paper has been significantly improved in thermal efficiency.For example,compared with the first-level reorganization cache,the hotspot temperature of the third-level reorganization cache is reduced by 10.10%-14.84%.Two reorder buffer architectures have been further designed to implement MPR methods,including hotspot-reducing Reorder Buffer?HRB?and hotspot-reducing Elastic Reorder Buffer?HERB?.In particular,HERB has a flexible dual area?FIFO area and Ro B area?buffer structure,with a configurable packet size and burst length of the target stream.Therefore,HERB can perform multi-stage reordering while reducing hardware overhead.Compared with the three architectures of Basic,NoCs'14^[52],and HRB,the operating frequency of HERB has been increased from 200 MHz to 300 MHz,and the area has been reduced by28.1%,29.4%,and 61.4%,respectively.?3?Design a global regulation NoC architecture based on reinforcement learning.In the Network-on-Chip,routing performance optimization is another research focus.Compared with the static routing scheme,the dynamic routing scheme can better reduce the data transmission delay of data packets under network congestion.Based on the Q-learning algorithm in machine learning,we globally control the network,improve the efficiency of data transmission,reduce hotspots,and ensure that the on-chip thermal performance while maintaining communication at a high speed,thereby ensuring chip reliability.Experimental results show that the network latency is reduced by 22.9%-49.5%compared to traditional routing algorithms.