The Implementation Of Physical Layer Scheduling And Interconnecting In TD-LTE System On The Board AMC2C6670

Ever since the third-generation mobile communicationsystem, LTE has become the essential new generation mobile communication system. It includes two kinds of standard, FDD and TDD. Based on the fundamentals of orthogonal frequency division multiplexing(OFDM) and multiple input multiple output(MIMO) technology, LTE system adopts the form of packet to tra nsmit data and it can theoretically achieve 100Mbit/s downlink peak rate and 50Mbit/s uplink peak rate in 20 MHz frequency bandwidth. Compared with the 3G communication system, LTE system increases an order of magnitude in the aspect of the overall complexity of the algorithm and the transmission performance. So a single processor can not meet the requirements of the real-time processing for large-scale and high speed data stream, distributed multi processor parallel processing is becoming an efficient way to enhance system performance. What a way can we choose to provide an effective、flexible and high bandwidth interconnect architecture, is becoming a new challenge during the design of 4G wireless communication system.The TDD-LTE experiment system mainlyconsists of the main-control board, the baseband board AMC2C6670 and the RF board. The baseband board AMC2C6670 is in charge of the physical layer processing. When the TDD-LTE experiment system is working, every millisecond sees a large amount of data tra nsmission between the baseband board DSP and the main-control board or between DSP and FPGA, both of them are included in the baseband board.Considering the requirements of the physical layer processing in TDD- LTE experiment system, a serial RapidIO interconnect scheme, at the core of TI’s TMS320C6670, is proposed in my paper to to solve the problem that exists in the multi-processor interconnection. Many experimental results have revealed the feasibility and the reliability of the interconnection scheme. For example, we send 256 KB of data with the configuration of 4× and 5Gbps, the transmission speed can be up to 10 Gbps even if we choose the DDR3 as our data memory storage between the transmitter and the receiver. Therefore the serial Rapid IO interconnect scheme is particularly appropriate to the new wireless base station system,such as TDD-LTE.My paper will be started from the following three aspects. First, the basic theory of serial RapidIO is introduced and a simplified SRIO test schematic diagram with its program flow is put forward through the study of the data interface in the TDD-LTE experiment system. Then there are some experiments, about the peripheral circuit and the amount of data, the storage medium etc, have been doneon the TMDXEVM6670 L evaluation board to research the performance of the Serial RapidIO link. Finally, the TDD-LTE experiment system selects NWrite or SWrite as its transmission mode. Now a Serial Rapid IO link has been designed and verified on the baseband board AMC2C6670. The verification test includes the connectivity between DSP and the main-control board or between the DSP and FPGA, NWrite transmission error rate and NWrite transmission rate. With the performance on the connectivity and reliability, it reveals that the serial RapidIO can meet the interface.requirements of the TDD-LTE experiment system.