The ASIC Implementation Of Ultra High Speed Parallel Stochastic Turbo Decoder

Turbo codes have become an attractive forward error correction scheme and are broadly adopted as channel coding scheme in the third generation, fourth generation and subsequent mobile communication systems. The implementation complexity of traditional high speed turbo decoder is very large, stochastic decoding that is inspired by stochastic computation is an alternative technique for high speed turbo decoder design. The signal data is represented by random sequences in stochastic turbo decoder. In this dissertation, the main research object is the ASIC design implementation and tape out for the fully-parallel stochastic turbo decoder.In this dissertation, the ASIC implementation is performed with the EDA tools from Synopsys and Mentor Graphics. Combined with the ASIC implementation of the fully-parallel stochastic turbo decoder, the dissertation describes and analyzes the related technologies of logic synthesis in the front end, physical design in the back end and chip verification. Meanwhile, the dissertation elaborates the logic synthesis and physical implementation process of the stochastic turbo decoder. In addition, we carry out the layout verifications for the stochastic turbo chip and perform the back-annotated dynamic timing simulation when the chip layout has been achieved. In the logic synthesis, we firstly provide a detailed description to the cell libraries and analyze the main design constraints which can be used to set the target of logic synthesis. Then we propose a synthesis scheme to the optimized stochastic turbo decoder. Finally, static timing analysis is applied to analyze the synthesized information without any timing violations. In the physical design process of the turbo decoder, we research deeply on the floorplanning, power network planning, clock tree synthesis and routing, and a brief description of placement, layout generation and ECO routing. In the chip verification stage, formal verification, static timing analysis and layout verification are discussed. In the end of the dissertation, timing simulation with the layout information is carried out to ensure the correctness of the design.Combined with the ASIC implementation of the design, we summarize some commonly used technologies for each stage of the ASIC flow. Furthermore, the ASIC implementation flow and related Tcl scripts for SMIC130 nm process, including logic synthesis, physical implementation and layout verification, are established. The design flow and scripts can be used as the design reference for the subsequent ASIC projects. The final parameters for the design layout which is fabricated by SMIC are summarized as follows:The fully-parallel stochastic turbo decoder is based on an algorithm which is named MAX-LOG-MAP and the code length is optional, ranging from 44 to 384. The implementation of this design is accomplished based on the SMIC130 nm 1P8M1TM process. This chip is a millions of standard gates scale design, and the layout area of the chip is 23.8mm2. The clock frequency of our design is up to 200 MHz, 100 MHz by default.