Research On 20-40GHz Wide-band Phase-locked Loop Frequency Synthesizer

Being the key component of the current electronic systems, the performance of frequncy synthesizer plays a decisive role in the whole system’s operation. Nowadays, with the rapid development of wireless telecommunication technologies, the frequency spectrum has been so fully exploited that scientists start to transfer their research focus to higher millimeter wave band. Hence, investigation on wide-band frequency synthesizer of outstanding operation performance in higher frequency band is of great value and practical significance. Under such circumstances, this thesis proposes to design a 20-40 GHz wide-band frequency synthesizer of excellent output power flatness and satisfying spurious suppression performance. The proposed frequency synthesizer’s functional frequency range contains the whole Ka wave band, so it can be extended to higher frequency wave band by means of frequency multiplying,frequency mixing or other frequency band extending methods.This thesis first briefly introduces the fundamental theory of PLL(Phase Locking Loop) frequency synthesizer and its performance parameters. Then the system scheme is established as “wide band PLL+frequency doubler” after analyzing the technical objectives proposed, discussing the advantages and shortcomings of different methods to realize wide band frequency synthesizer and reviewing the operation properties of chips that may be used in the circuits.The project is divided into three parts to be studied:(1)chip selection, cavity design, circuits design and debugging of 10-20 GHz wide band PLL frequency synthsizer;(2)chip selection, circuits design and fabrication, experiment results analysis of the frequency doubling section;(3)realization of filtering the VCO’s output 10-20 GHz signal and the doubled 20-40 GHz signal. The earlier stage work includes selection of switch chip, circuits design of filters and appropriately dividing the frequency band so that the majority of spurious can be filtered. The later stage work mainly concerns circuits design, cavity fabrication and circuits debugging.After every circuit unit is debugged, we connect them together and repeat the debugging procedure in order to reach the satisfying results that meet the technical objectives proposed above. In the last part of this thesis, we retrospect on the problems encountered during the experiments and analyze why some technical objectives are not accomplished considering technique prospective and scheme design prospective. We also put forward methods that may improve the deficiencies of current system scheme design.