Design Of Wide Band And Low Noise Frequency Synthesis System Based On PLL For Wireless Communication Application

With the development of wireless communication technology,more and more frequency bands are occupied in wireless communication.Therefore,the requirements for the carrier of the wireless transceiver on frequency accuracy and spectrum purity are getting higher and higher.Consequently,it also becomes difficult to design the frequency synthesizer that meets the metrics.Around the frequency synthesizer based on the phase-locked loop,extensive research and design work has been done.Focus on the low phase noise,automatic frequency calibration and high-speed frequency doubling,the thesis achieves the following results.Firstly,considering the main loop parameters of phase-locked loop,an application called“PLL＿Parameter”is developed.The application has the function of repeated iteration.As the result,it is not only suitable for the pre-design of the general-purpose frequency synthesizers based on PLL,but also can verify the rationality of the loop parameters provided by the users.Secondly,aiming at the phase noise of the oscillator,a voltage-controlled oscillator covering 1.5-3GHz frequency range is implemented.In order to improve the phase noise,the quality factor of resonant tank is optimized.Furthermore,an automatic frequency calibration approach suitable for non-uniform frequency bands is proposed.A counting window initializer is performed before the AFC process.A frequency error range of less than 1MHz within the entire VCO frequency range is achieved.The shortest convergence time is no more than 10μs after adding the initializer.In order to provide 3-6GHz output clock,a high-speed frequency doubler is proposed and connect to the output of the VCO.The frequency doubler combines logic operations and CML data selector.On the basis of the theoretical analysis and technical optimization,the thesis implements a fractional frequency synthesizer covering the whole Sub-6GHz frequency range in 0.13μm CMOS process.The results of post-layout simulation indicate that under the output frequency of 1.5GHz,the lowest in-band phase noise is-123.1d Bc/Hz,and the out-of-band phase noise can achieve-140.9d Bc/Hz@1MHz.The power consumption of the whole chip is about 427.2m W,and the VCO wastes about 483.1m W for ultra-low phase noise,accounting for about 90%of the overall power consumption.The optimal integral jitter is about 89.2fs,and the corresponding Fo M_J is about-234.7d B.Considering the load capacity of the frequency synthesizer,a high slew rate unity-gain buffer and a wideband power amplifier are implemented in 0.18μm Si Ge Bi CMOS process and 0.25μm CMOS process,respectively.The high slew rate unity-gain buffer is used to improve the drive capability of the low frequency clock.It can achieve a slew rate of above 1900V/μs.The wideband power amplifier is used to amplify the power of the high frequency signal.It can achieve a power gain of no less than 10d B within the frequency range of 0.2-10GHz.