Hardware/Software Co-design Of AC-3 Decoder Based On PowerPC

Production and development of digital media technology, have greatly improved the quality of life. With the constantly proposing of new technology, computing amount involved is growing. In order to meet the basic requirement of real-time processing in digital media technology, it is necessary to optimize the various technologies for process of data. And it’s worthy to realize that different ways of implementation have a significant effect on real-time.Considering that the AC-3 decoding of audio field in digital media technology has a large computing amount, various ways of implementation of the AC-3 decoder are researched in this thesis firstly. For the diversity in the field of embedded applications, an AC-3 decoder is implemented using loosely coupled hardware/software co-design technology, based on a SOPC(System on Programmable Chip) with PowerPC processor. The hardware accelerator is connected to the system in two ways: the usual Processor Local Bus(PLB) interface and dedicated Auxiliary Processor Unit(APU) interface in PowerPC. And some tests are executed for the improvement of decoding effect and the effect comparing of two interfaces. The main content of this thesis includes the following aspects:First, the SOPC hardware structure with PowerPC processor is determined. For the hardcore such as PowerPC processor, PLB and Flash controller, the facilities and configuration are researched. For the Σ-ΔDAC module, relevant design, package and verification are completed. Then hardware system is set up in Xilinx Software Studio(XPS).To realize the high speed communication between the PowerPC processor and hardware accelerator, the dedicated APU interface is researched in details. The signals’ definition, instruction’ structure and execution, and the timing are analyzed. And the method of APU’s attachment and configuration is mastered.Then, based on personal computer, the AC-3 decoding project is debugged and verified. And after some transplanting work, the project works on the SOPC. The performance evaluation results show that a compute-intensive module, IMDCT, costs a lot of time. When considering hardware/software co-design, this part should be implemented in hardware.At last, an applicable IMDCT hardware accelerator is chosen, and packaged in PLB and APU interfaces. After attachment to SOPC, corresponding configuration and software modification, the AC-3 hardware/software co-decoder is implemented. The new performance evaluation results indicate that compared with software decoder, the decoding efficiency increases 16% in the hardware/software co-decoder with APU hardware accelerator. And compared with the hardware/software co-decoder using PLB hardware accelerator, processing time per frame of APU interface decoder decreases 0.11 ms, which means that the data communication efficiency increases 25%.